Multiplier, digital filter and synthesis device
A technology of multipliers and multipliers, which is applied in the field of multipliers for multiplication of multipliers and multiplicands, and can solve problems such as reducing circuit scale.
Inactive Publication Date: 2010-11-10
PANASONIC CORP
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Problems solved by technology
A multiplier using Booth's algorithm can usually reduce the circuit size
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Abstract
The invention provides a multiplier, digital filter, signal processing device, composition device, composition program and composition program recording medium.Conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased because a bit extension is performed when the multiplier is adapted to an unsigned multiplication. A multiplication circuit of the present invention is provided with a first Booth encoder (1) for encoding lower-order several bits of a multiplier according to first rules of encoding using a Booth algorithm, and a second Booth encoder (5) for encoding most-significant several bits of the multiplier according to second rules of encoding using a Booth algorithm, which are different from the first rules of encoding, and thereby the most-significant several bits of the multiplier are encoded using the Booth algorithm which is different from thatfor the lower-order several bits.
Description
Multiplier, digital filter and synthesis device technical field The present invention relates to a multiplier for performing operations on binary numbers, in particular to a multiplier for performing multiplication operations on an unsigned multiplier and a multiplicand. Background technique A multiplier is one of the necessary arithmetic units used in most digital signal processing. In the case of multiplication between two's complement numbers, Booth's algorithm is often used in order to reduce the number of partial products. A multiplier using Booth's algorithm can generally reduce the circuit scale. In addition, even in unsigned multiplication, since the input sign bit is extended, Booth's algorithm can be applied. So far, various patents have been filed for the structure of an arithmetic multiplier using Booth (for example, refer to Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4). FIG. 6 is a diagram showing a conventional example...
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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/533
CPCG06F7/5338G06F7/5324
Inventor 永野孝一
Owner PANASONIC CORP
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