85 results about "Two's complement" patented technology

Systems and methods related to concealing mathematical and logical operations in software. Mathematical and logical operations are disguised by replacing them with logically equivalent expressions. Each equivalent expression has at least two expression constants whose values are based on scaling and bias constants assigned to variables in the original mathematical or logical operation. Each of the expression constants may also be based on additive or multiplicative inverses modulo n of the scaling and bias constants. By replacing the original operations with more complex but logically equivalent expressions containing variables that also involve more operations, the true nature of the original operations is disguised.

A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q₀≠q₁ for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s₀ and s₁ when information sequences d₀ and d₁ resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s₀=s₁=6, in a third block, and two's complement q₀ of a sum of code sequences c₀ up to a time when the code states are equal to each other is “0” while two's complement q₁ of a sum of code sequences c₁ up to that time is “1”. That is, the condition that q₀≠q₁ is met. The code sequence can be applied to a recorder/player or encoder.

The invention provides a multiplier, digital filter, signal processing device, composition device, composition program and composition program recording medium.Conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased because a bit extension is performed when the multiplier is adapted to an unsigned multiplication. A multiplication circuit of the present invention is provided with a first Booth encoder (1) for encoding lower-order several bits of a multiplier according to first rules of encoding using a Booth algorithm, and a second Booth encoder (5) for encoding most-significant several bits of the multiplier according to second rules of encoding using a Booth algorithm, which are different from the first rules of encoding, and thereby the most-significant several bits of the multiplier are encoded using the Booth algorithm which is different from that for the lower-order several bits.

In a power amplifier driven by a pulse width modulation (PWM) signal, a first pair of drive pulses opposite in level to each other is formed from a first pulse width modulation signal whose quantization level corresponds to its pulse width and supplied to a first push-pull circuit (15). A second pair of drive pulses opposite in level to each other is formed from a second pulse width modulation signal whose two's complement of quantization level corresponds to its pulse width, and supplied to a second push-pull circuit (16). A speaker (19) is connected between the first and second push-pull circuits (15 and 16). A deviation between potentials at the output terminals of the first and second push-pull circuits (15 and 16), respectively, is detected. When a deviation is detected, the push-pull circuits are substantially stopped from operating.

A multi-bit computing circuit for computing-in-memory applications is controlled by an input port and includes a memory cell array and a capacitor sharing unit. The memory cell array includes a plurality of memory cells connected to the input port. The memory cells store a weight which is formed in two's complement. The capacitor sharing unit includes a plurality of switches, a plurality of capacitors and a sense amplifier. The switches are electrically connected to the memory cells, respectively. The capacitors are electrically connected to the switches, respectively. The sense amplifier is electrically connected to the capacitors and generates a total operational value. The capacitors are located among the switches and the sense amplifier, and the switches are switched to enable the total operational value to be equal to the input value multiplied by the weight. The present disclosure utilizes 8T SRAM cells without an extra DAC structure.

A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of a carry save adder and the output of the adder are input to convert the data into twos complement representation data, and the twos complement representation data is shifted a certain bit number (determined on the basis of the radix of the operation) to use the shifted data for a partial remainder of the next digit. Hence, a large number of parts such as registers of a divisor and a partially extracted square root can be commonly used in a divider and a square root extractor to realize an effective and high performance arithmetic unit.

A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value of a second operand, and an arithmetic inverse of the second operand value, in response to the sign bit of the first operand. This logic circuitry is arranged to operate according to 2's-complement integer arithmetic, by also including invert-and-increment circuitry to produce a 2's-complement inverse of the second operand. A comparator determines whether the second operand is at a maximum 2's-complement negative value, in which case the arithmetic inverse is selected to be a hard-wired maximum 2's-complement positive value. Logic circuitry is also included in the co-processor to execute an instruction to multiple the signs of two operands; this logic circuitry is realized as an exclusive-OR function operating on the sign bits of the operands, and a multiplexer for selecting between digital words of the values +1 and −1 in response to the exclusive-OR function. The logic circuitry can be arranged in multiple blocks in parallel, to provide parallel execution of the instruction in wide datapath processors.

A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator comprises a series of stages. Each stage includes a shift register for serially receiving samples of the signal. Each stage further includes a two's complement generator for producing a two's complement of a first sample of the signal and a first multiplexer for selecting between a first sample of the signal and the two's complement of the first sample. A first adder then generates a sum of a second sample of the signal and the first sample and a difference of the second sample and the first sample and supplies the sum and the difference to the shift register of the next stage. In one embodiment the shift registers are implemented in random access memory.

An MRI apparatus includes: an RF coil to which analog RF pulse signals are applied; an RF pulse generating circuit which generates said analog RF pulse signals; and a magnetic resonance signal receiving circuit which receives analog magnetic resonance signals and converts these signals into baseband digital magnetic resonance signals, said RF pulse generating circuit comprising: a carrier signal generator which generates a digital carrier signal having a predetermined number of bits; a digital modulator which modulates said digital carrier signal with a digital envelope signal, thus generating digital RF pulse signals; a digital-analog converter which converts said digital RF pulse signals into the analog RF pulse signals; and an inversion unit which generates a digital inverted carrier signal having a two's complement relationship with said digital carrier signal and sends the digital inverted carrier signal to said magnetic resonance signal receiving circuit, said magnetic resonance signal receiving circuit comprising: an analog-digital converter which converts the analog magnetic resonance signals into digital magnetic resonance signals having a predetermined number of bits; and a digital demodulator which demodulates said digital magnetic resonance signals with said digital inverted carrier signal, thus converting these signals into the baseband digital magnetic resonance signals.

It is a new multiplier reconstructing algorithm which comprises the following: two N bit two's complement number with signs or number without signs which are used as multiply operation numbers into two input ends of the multiplier; to symmetrically divide the two N bit multiply operation numbers into half of the original bit width; to input the two N bit operation number N/2 high order and N/2 low order into two subtracters, wherein, one is to finish one operation number calculation and the other is to finish the other operation number low order minus high order calculation; to multiply two N bit numbers and get R2, and to multiply low order by low order input into multiplier and get R0 and the two output numbers from two subtracters is inputted into N/2 bit multiplier 3 and get the result R1;The multiplier results R2 and R0 are joint into 2N bit number and the right No. N/2 is in alignment with first bit of R2,R1 and R0 the additive result of which is used as multiply result to be outputted.

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e.g., radix-4) Booth recoding on B generates “n” multiplication factors, where “n,” an integer, is approximating one half of the number of the multiplier bits. “n” partial products are generated using the “n” multiplication factors as multipliers of A. Then, a multiplication tree is formed using radix-m Booth encoding. The multiplication tree includes multiplier bits associated to generate a multiplication factors. In the event of a negative multiplication factor, a two's complement of A is formed by inverting the bits of A and associating a sticky “1” to complete the two's complementation. Furthermore, multiplication factors are reduced in multiple stages to a form sum and carry components of a pre-determined length. The additive inverse of A×B is formed by using novel techniques to calculate the product of A and −B.

The invention discloses a discrete cosine transform (DCT) implementation method and system based on randomized computation. The method comprises the following steps: mapping the ratio of an image transform unit (TU) to DCT into a decimal within a preset range, and transforming the decimal into a random sequence; transforming the random sequence into a randomized computation domain sequence, and computing by using a randomized computation multiplier and a randomized computation adder; transforming a computed result into a two's complement form in order to realize DCT. By adopting the method and the system, the hardware consumption can be lowered greatly, and the working clock frequency of the system is increased.

In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second halves of a ten-bit message, respectively, from two's-complement-to-sign-magnitude format. The reconfigurable 2TSM converter then generates a ten-bit sign-magnitude message based on the conversions of the two non-reconfigurable 2TSM and a carry-over bit. In another embodiment, a reconfigurable sign-magnitude-to-two's-complement (SMT2) converter comprises the reconfigurable 2TSM described above. The reconfigurable SMT2 is selectively configurable to operate in (i) a five-bit mode to convert two five-bit messages concurrently and (ii) a ten-bit mode to convert one ten-bit message at a time.

A dynamic package scale includes a dynamic intelligent data acquisition device and a dynamic operating system integrating weighing, code scanning and volume detection. The dynamic intelligent data acquisition device adopts three-section type modular design, including a caching section, a weighing, code scanning and volume detection section and a code complementing section; and the dynamic operating system controls start-stop transmission and transmission distance of three sections of conveyer belts according to a detection result of the weighing, code scanning and volume detection section, sothat packages can be rapidly lined up and checked in an ordered manner, and a situation of missing detection is prompted in time through an alarm to perform code complementing. The dynamic package scale provided by the invention is easy to operate and is high in efficiency and precision, greatly improves work efficiency, and avoids unnecessary resource waste.