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Multiplier, digital filter, signal processing device, synthesis device, synthesis program, and synthesis program recording medium

A technology of multipliers and multipliers, which is applied in the field of multipliers in which multipliers and multiplicands are multiplied, and can solve problems such as reducing circuit scale.

Inactive Publication Date: 2009-03-11
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A multiplier using Booth's algorithm can usually reduce the circuit size

Method used

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  • Multiplier, digital filter, signal processing device, synthesis device, synthesis program, and synthesis program recording medium
  • Multiplier, digital filter, signal processing device, synthesis device, synthesis program, and synthesis program recording medium
  • Multiplier, digital filter, signal processing device, synthesis device, synthesis program, and synthesis program recording medium

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Embodiment approach 1

[0078] Hereinafter, a multiplier according to Embodiment 1 of the present invention will be described with reference to FIG. 1 .

[0079] FIG. 1 is a block diagram of a multiplier that receives an unsigned multiplier as an input according to the first embodiment. In Fig. 1, 1 is the first Booth encoder, 2 is the first partial product generation circuit using the output of the first Booth encoder 1 to generate the partial product, 5 is the second Booth encoder, and 6 is the first partial product generation circuit using the output of the first Booth encoder 1. 2. A second partial product generation circuit for generating a partial product from the output of the Booth encoder 5 . In addition, 3 is an adding circuit for adding the output of the first partial product generating circuit 2 and the output of the second partial product generating circuit 6, and 4 is bit-expanding the input multiplier and distributing it to the first Booth encoder 1 and 2 bit extension distribution ci...

Embodiment approach 2

[0101] A multiplier according to Embodiment 2 of the invention will be described using FIG. 2 .

[0102] FIG. 2 is a block diagram showing a multiplier that receives an unsigned multiplier as an input according to the second embodiment. In FIG. 2 , the same symbols as those in FIG. 1 denote the same or corresponding parts. In addition, 7 is the third Booth encoder which encodes the input signal according to the same symbolization rule as the first Booth encoder, and 8 is the third part which uses the output of the third Booth encoder 7 to generate the partial product The product generating circuit 9 is a selection circuit for selecting and outputting either the output of the second partial product generating circuit 6 or the output of the third partial product generating circuit 8 .

[0103] In FIG. 2 , the difference from the multiplier of the first embodiment shown in FIG. 1 is that a third Booth encoder 7 , a third partial product generation circuit 8 , and a selection cir...

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Abstract

The invention provides a multiplier, digital filter, signal processing device, composition device, composition program and composition program recording medium.Conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased because a bit extension is performed when the multiplier is adapted to an unsigned multiplication. A multiplication circuit of the present invention is provided with a first Booth encoder (1) for encoding lower-order several bits of a multiplier according to first rules of encoding using a Booth algorithm, and a second Booth encoder (5) for encoding most-significant several bits of the multiplier according to second rules of encoding using a Booth algorithm, which are different from the first rules of encoding, and thereby the most-significant several bits of the multiplier are encoded using the Booth algorithm which is different from that for the lower-order several bits.

Description

technical field [0001] The present invention relates to a multiplier for performing operations on binary numbers, in particular to a multiplier for performing multiplication operations on an unsigned multiplier and a multiplicand. Background technique [0002] A multiplier is one of the necessary arithmetic units used in most digital signal processing. In the case of multiplication between two's complement numbers, Booth's algorithm is often used in order to reduce the number of partial products. A multiplier using Booth's algorithm can generally reduce the circuit scale. [0003] In addition, even in unsigned multiplication, since the input sign bit is extended, Booth's algorithm can be applied. [0004] So far, various patents have been filed for the structure of an arithmetic multiplier using Booth (for example, refer to Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4). [0005] Figure 6 is a diagram showing a conventional example of a m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/533
CPCG06F7/5324G06F7/5338
Inventor 永野孝一
Owner PANASONIC CORP
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