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Multiplier restructuring algorithm and circuit thereof

A technology for reconstructing algorithms and multipliers, which is applied in the field of microelectronics, and can solve the problems of multiplier computing power difficulty, speed, power consumption and area that cannot be satisfied

Inactive Publication Date: 2005-01-19
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, it is very difficult for the existing multipliers based on the Booth-Wallace tree fast algorithm to achieve 64-bit or even higher computing power, and the speed, power consumption and area cannot meet the requirements of future technologies.

Method used

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  • Multiplier restructuring algorithm and circuit thereof
  • Multiplier restructuring algorithm and circuit thereof
  • Multiplier restructuring algorithm and circuit thereof

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Embodiment Construction

[0025] see figure 2 , a novel reconstruction algorithm multiplier circuit implementation structure of the present invention, including:

[0026] One input multiplication operand register 20, this register 20 preserves two N-bit multiplication operands of external input;

[0027] An N-bit novel reconstruction algorithm multiplier circuit 10, which is connected to the input multiplication operand register 20.

[0028] The N-bit novel reconstruction algorithm multiplier circuit 10 includes a multiplication operation module 11 , an intermediate data processing module 12 , and an addition and summation operation module 13 . The multiplication operation module 11, the intermediate data processing module 12 and the addition and summation operation module 13 are connected in sequence.

[0029] The first subtractor 114 of two N / 2 positions, the second subtractor 115 and the first multiplier 111 of three N / 2 positions, the second multiplier 112, and the third multiplier are arranged ...

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Abstract

It is a new multiplier reconstructing algorithm which comprises the following: two N bit two's complement number with signs or number without signs which are used as multiply operation numbers into two input ends of the multiplier; to symmetrically divide the two N bit multiply operation numbers into half of the original bit width; to input the two N bit operation number N / 2 high order and N / 2 low order into two subtracters, wherein, one is to finish one operation number calculation and the other is to finish the other operation number low order minus high order calculation; to multiply two N bit numbers and get R2, and to multiply low order by low order input into multiplier and get R0 and the two output numbers from two subtracters is inputted into N / 2 bit multiplier 3 and get the result R1;The multiplier results R2 and R0 are joint into 2N bit number and the right No. N / 2 is in alignment with first bit of R2,R1 and R0 the additive result of which is used as multiply result to be outputted.

Description

technical field [0001] The invention belongs to the design of high-speed, low power consumption and reconfigurable structural integrated circuits in the field of microelectronics, in particular to a novel multiplier reconfiguration algorithm and circuit. Background technique [0002] Multiplication is frequently used in digital signal processing, including signal processing, communication and consumer electronics, so multipliers are used in application-specific integrated circuits (ASICs), general-purpose digital signal processors (DSPs) and advanced microprocessors ( CPU) are widely used. There are also many ways to implement multiplication with hardware, usually there are shift-accumulate array multipliers and fast multipliers using Booth algorithm and Wallace tree compression structure. [0003] In general-purpose instruction processors (DSP, CPU), the multiplier is usually located on the critical path of timing, which is the bottleneck of pipeline balance, and is also t...

Claims

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Application Information

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IPC IPC(8): G06F7/38G06F7/44
Inventor 李莺陈杰
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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