Method and system for video decoding

Abstract

The invention provides a method and a system for video decoding. The method comprises the following steps: 1, carrying out entropy decoding on first primary data, saving the data after the entropy decoding into a first cache unit and obtaining first entropy decoding data; 2, carrying out entropy decoding on second primary data, saving the data after the entropy decoding into a second cache unit and obtaining second entropy decoding data; while carrying out entropy decoding on the second primary data, extracting the first entropy decoding data, reordering residual coefficient included in the first entropy decoding data, saving the reordered result in a third cache unit and obtaining first anti-scanning data; and 3, extracting the first anti-scanning data, carrying out time-frequency conversion on the first anti-scanning data, and obtaining the first residual value corresponding to the first entropy decoding data. The method and system can reduce waiting time while carrying out data processing in video decoding process in the prior art and achieves the aim of improving the processing capacity of the video decoding system.

Description

technical field [0001] The present invention relates to the technical field of multimedia video transmission, in particular to a method and system for video decoding. Background technique [0002] In the application-specific integrated circuit (ASIC) solution of video decoding, a good hardware pipeline architecture is the basis for ensuring chip cost and power consumption. Now the vc0830 project uses hardware decoding IP (7170), which supports full-speed SD decoding only under the normal operating frequency (100Mhz-133Mhz), but in the process of 720P resolution decoding, it is limited by the back-end technology and power consumption increase, etc. The problem is that the working frequency of the IP is difficult to increase a lot, so full-speed decoding cannot be performed, resulting in the shrinking of the chip function. [0003] figure 1 It is a schematic diagram of a decoding process in the prior art. Such as figure 1 , the original code stream of the decoded data is s...

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Problems solved by technology

[0005] Therefore, in the decoding pipeline of the prior art, there is a certain waiting time on the entropy decoding module 2 and the anti-scanning module 3, which makes it difficult to improve the processing capacity of the decoding work, and cannot perform full-speed decoding, which affects chip performance and cost

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