Memorizer with disabling circuit and method for disabling memorizer

Abstract

The invention discloses a memorizer with a disabling circuit, which comprises a memorizer array and a disabling circuit. The memorizer array comprises a data output end and an output enabling end. The disabling circuit is coupled to the data output end and the output enabling end. The disabling circuit comprises a fuse and an output end, wherein the disabling circuit determines the logic state ofthe output end according to the logic states of the output enabling end and the data output end when the fuse is not brunt out, and the disabling circuit leads the output end to be under a high-impedance state when the fuse is brunt out. Therefore, an external circuit can not read or write the memorizer array. Meanwhile, the invention further discloses a method for disabling the memorizer.

Description

technical field [0001] The present invention relates to a memory, and more particularly to a memory with a disabling circuit capable of disabling the memory when the memory is defective. Background technique [0002] With the development of integrated circuit technology and the improvement of device density, a wafer for memory applications can simultaneously produce multiple dies containing millions of electronic components. Usually, in the production process of these crystal grains, a wafer process is performed first, and processes such as deposition, photolithography, or etching are performed on some or all chips on the wafer at the same time. After the wafer is fabricated, back-end processes such as dicing and packaging are performed. [0003] Generally speaking, before the finished wafer is packaged, it is necessary to perform various electrical function tests on each die on the wafer to determine whether there are damaged dies and ensure that they are functional when t...

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