A method and system for realizing multi-standard digital filtering

A technology of digital filtering and implementation method, which is applied in the direction of digital technology network, impedance network, electrical components, etc., can solve problems such as large amount of calculation, limited digital signal processing speed, and difficulty in data throughput rate meeting real-time requirements, so as to reduce consumption , the effect of reducing resource consumption

Active Publication Date: 2015-09-16
ZTE CORP
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Problems solved by technology

But on the other hand, due to the limited speed of subsequent digital signal processing, especially for some synchronous demodulation algorithms, the amount of calculation is very large, and it is difficult to meet the real-time requirements when the data throughput rate is too high. The subsequent data flow is decelerated

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  • A method and system for realizing multi-standard digital filtering
  • A method and system for realizing multi-standard digital filtering
  • A method and system for realizing multi-standard digital filtering

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Embodiment Construction

[0035] The main idea of ​​the present invention is to propose a realization scheme of a sampling rate self-adaptive digital filter. The cycle that appears is 2^n clock cycles. The sampling rate is identified by judging the data synchronization frame header, and the minimum number of shared sample point cycles for each sample point cycle is determined. Within the minimum shared sample point cycle number of clock cycles The multiplication and accumulation is completed, so that the filter performs adaptive filtering on the integer multiple sampling rate data.

[0036] Based on the above ideas, the present invention provides a method for implementing multi-standard digital filtering, which specifically includes the following steps:

[0037] Step A: Identify the data sampling rate according to the data frame header;

[0038] Step B: Obtain the greatest common divisor of the period of each sampling point;

[0039] Step C: performing polyphase decomposition on the filter coefficien...

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Abstract

The invention relates to a multi-standard digital filtering implementation method and system, wherein the method comprises the following steps of: identifying data speed according to data frame head; respectively calculating sample point periods of the identified signals with different data speeds, and determining a minimum common sample point period number of each signal; performing multi-phase decomposition on a filter, and completing multiplication-accumulation operation of each phase in clock periods of the minimum common sample point period number. The invention automatically determines the sampling rate by judging the data frame head, without the selection of switch, and reduces the consumption of the clock domain by the using of the same operating clock; furthermore, the data with different bandwidth shares the multiplication-accumulation operation so that the resource consumption is greatly reduced.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a method and system for realizing digital filtering of multi-standard data. Background technique [0002] Multi-rate signal processing is the key to digitization of signal processing in software radio. The application of the band-pass sampling theorem hopes to improve the sampling bandwidth and signal-to-noise ratio by increasing the sampling rate. But on the other hand, due to the limited speed of subsequent digital signal processing, especially for some synchronous demodulation algorithms, the amount of calculation is very large, and it is difficult to meet the real-time requirements when the data throughput rate is too high. The subsequent data flow is decelerated. [0003] Multi-rate signal processing is essentially a process of resampling discrete sequences after sampling. Many applications of multi-rate signal processing are implemented based on filter b...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03H17/02
Inventor 廖颍川
Owner ZTE CORP
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