33 results about "Polyphase decomposition" patented technology

Sample rate converters are known, and are used to convert a signal with a first sample rate (sampling frequency) into a signal with a second sample rate (sampling frequency). To obtain a flexible sample rate converter with sampling frequencies that are not known beforehand, until now only sample rate converters with very high intermediate sampling frequencies are known. The invention provides a flexible sample rate converter, which is able to handle unknown input and output sampling frequencies. This is achieved by using polyphase decomposition filter means in combination with interpolation means.

The invention provides an antenna arraying full-spectrum correlated combining system based on a broadband signal frequency domain and aims to provide a frequency domain based arraying system capable of saving hardware computing resources and overcoming phase ambiguity. The technical scheme includes that the antenna arraying full-spectrum correlated combining system is implemented according to that an A / D (analog / digital) module is used for sampling inputted broadband medium-frequency analog signals; obtained digital medium-frequency signals are subjected to sampling clock full-period delay by a delay module according to N antenna signal time delay estimation values fed back by a correlated combining module, then subjected to frequency conversion by a DDC (digital down converter ) module, polyphase decomposition by an analysis module to obtain M falling-rate narrow-band branches with uniform frequency domain ranges, polyphase correlation, time delay estimation and feedback, fractional time delay correction and polyphase combining by a correlated combining module, polyphase synthesis by a synthesis module, and finally are outputted to a demodulation receiver through a DUC (digital up converter) module and a D / A (digital / analog) module. The antenna arraying full-spectrum correlated combining system based on the broadband signal frequency domain solves the problem of phase ambiguity through integer multiples of sampling clock delay and fractional delay compensation.

The invention provides a method and a device for digital down converter and filtering extraction, belonging to the field of signal and information processing. The method comprises the following steps: receiving a middle frequency digital signal, and carrying out polyphase decomposition processing with a polyphase decomposition factor of n on the middle frequency digital signal to obtain n paths of signals subjected to the polyphase decomposition processing and output the signals; receiving n paths of signals subjected to the polyphase decomposition processing, carrying out mixed frequency processing on each path of signal subjected to the polyphase decomposition processing to obtain n paths of signals subjected to the mixed frequency processing and output the signals; and receiving n paths of signals subjected to the mixed frequency processing and carrying out filtering extraction processing on the n paths of signals subjected to the mixed frequency processing according to an extraction factor m to obtain n / m paths of digital down converter signals, wherein m, n and n / m are natural numbers which are not equal to zero, and m is more than or equal to n. The device comprises a polyphase decomposition circuit, a mixed frequency circuit and a filtering extraction circuit. The scheme reduces the operation complexity, improves the stability of the processor, and effectively improves the precision and real-time property of the operation at the same time.

The invention discloses a low-consumption digital decimation filter bank with variable decimation multiples and a digital decimation and filtering method. The low-consumption digital decimation filter bank and the digital decimation and filtering method are used for the filtering and the decimation of data. The filter bank comprises a first stage, a second stage and a third stage, wherein the first stage is a cascading comb-shaped integrating filter which is used for achieving the decimation movement with large multiples, the second stage is a half-band filter of at least one stage which is used for achieving the decimation movement of the second stage, the third stage is a compensating filter which is used for compensating pass band damping and carrying out filtering decimation movement, and the first stage is the cascading comb-shaped integrating filter with variable decimation multiples in a non-recursion mode. The method comprises the steps of determining decimation ratios and the system structure of the decimation filter bank, decomposing the transfer function of the cascading comb-shaped integrating filter, selecting the decimation ratios meeting requirements to for combination and carrying out multi-phase decomposition on the cascading comb-shaped integrating filter, the half-band filter and the compensating filter. The low-consumption digital decimation filter bank with the variable decimation multiples and the digital decimation and filtering method have the advantages that the number of registers working close to high frequency can be reduced, resource consumption is reduced, and power dissipation is reduced.

The invention provides a frame detection method for an orthogonal frequency division multiplexing ultra-wideband system. The method comprises the following steps: performing 1:4 serial-parallel conversion on a received sampling data of an analog-to-digital converter; dividing the data subject to the serial-parallel conversion into two paths; utilizing an optimized matching filter coefficient to perform matching filtering on one path of the data, performing a delaying multiplying operation on a matching filtering result, and then utilizing a weighting coefficient in an exponential form to perform accurate matching filtering on a delaying multiplying result so as to acquire a decision, and finally performing quadruple downsampling treatment on the decision, wherein multiphase decomposition is used for reducing the calculation quantity of weighting accumulation; and estimating the power of the other path of the data to acquire an estimated power value and then performing the quadruple downsampling treatment on the estimated power value, wherein the calculating quantity is reduced since the multiphase decomposition is used for realizing the power estimation and the quadruple downsampling treatment, and a recursive algorithm is used for realizing each multiphase component; and finally, inputting calculated results of the two paths of the data into a comparator, and judging whether a frame exists.

The invention provides a real-time broadband spectrum analysis and storage method and device. The invention relates to a real-time broadband spectrum analysis and storage method, which comprises the following steps of: carrying out digital processing on a broadband radio frequency signal to obtain a broadband baseband complex signal; carrying out multiphase decomposition on the broadband baseband complex signal to obtain multiphase branch signals, and carrying out serial pipeline FFT calculation on each phase branch signal; selecting a twiddle factor, and performing complex multiplication on the serial pipeline FFT calculation result of each phase of branch signal and the twiddle factor; performing parallel pipeline FFT calculation on a complex multiplication result of the multi-phase branch signal, and then performing logarithmic operation to obtain real-time spectrum data; caching and storing real-time spectrum data in a non-volatile memory in real time. According to the invention, full-parallel FFT calculation is directly carried out on the broadband signal acquired by the high-speed ADC, the frequency spectrum of the GHz-level broadband signal can be calculated in real time, and real-time frequency spectrum data can be recorded in a gapless and lossless manner.

The invention provides a method for realizing a high-order FIR filter based on an FPGA, used for solving the technical problem of excessive occupation of the high-order FIR filter to logic units in the FPGA in the existing method for realizing high-order FIR multiphase filtering. The method comprises the following steps: selecting parameters of a prototype filter; designing the prototype filter h (n); performing multiphase decomposition on the prototype filter h (n) to obtain multiphase filters; performing module division on each multiphase filter; storing coefficients of the multiphase filters in a module ROM; reading the coefficients of the multiphase filters in the module ROM; caching and reading input data by read-write enable, a write address control signal and a read address control signal of a module RAM obtained by system clock control; and performing multiplication and addition operations on the coefficients of the multiphase filters and the input data by using a multiplication accumulation module, and outputting an operation result. The method provided by the invention is little in occupation of the logic units in the FPGA, simple, efficient and is easy to realize.

The invention belongs to the field of digital image processing, and aims to provide a method for eliminating moiré patterns in screen shots that do not exist in the prior art, so as to realize the elimination of moiré patterns in screen shot images. The technical solution adopted by the present invention is to provide a multi-phase layer decomposition model based on the multi-channel decomposition method for eliminating moiré in screen-shot images, and use the model in the Y channel to realize the desalination of moiré color stripes and high-frequency parts ; Input the obtained results into an improved Laplacian filter to further eliminate the color fringes; finally, apply the multi-phase decomposition layer model to the RGB channels of the results obtained in the previous step to obtain the final result. The invention is mainly applied to digital image processing occasions.

A multi-antenna channel estimation method based on polyphase decomposition includes: receiving frequency domain received signals transformed using discrete fourier transformation (DFT) in pilot symbols; performing phase correction on the frequency domain received signals; performing polyphase decomposition on the frequency domain received signals which are corrected using phase correction and acquiring polyphase signals; performing interpolation on the polyphase signals and acquiring the estimation values of the multi-antenna channel parameters with various linear combinations on each frequency; acquiring decorrelation array based on the pilot structure of the transmission antenna and decorrelating the estimation values of the multi-antenna channel parameters with various linear combination on each frequency using the decorrelation array and acquiring channel parameters of the pilot symbols on each frequency; acquiring channel parameters of data symbols based on the channel parameters of the pilot symbols. With the present invention, the inversion problem in multi-antenna channel estimation is avoided with lower complexity, and results of the multi-antenna channel estimation method become more accurate since the DFT and filtering are performed in the interpolation after polyphase decomposition.

The invention provides a linear distortion correction method of a time interleaved analog-digital converter based on multiphase decomposition having low computational complexity. The method comprises the following steps: expressing spectral characteristics of a channel by a transfer function, then mapping the spectral characteristics into frequency response of a high order differentiator, carrying out multiphase decomposition processing on the constructed differentiators separately, providing an equivalent TIADC analysis module based on a multiphase structure, and extracting crosstalk and errors from an out[ut signal according to the model to complete multichannel correction. Experiments prove that the method has low requirements on the working speed of a correction filter, is simple and feasible, good in compensation effect and has universality to the correction of general frequency distortion errors.

The invention provides an approximately completely reconstructed satellite-borne low-complexity non-uniform bandwidth digital channelization device, which is used for solving the technical problems ofhigh reconstruction error, wide protection interval and high calculation complexity of the existing satellite-borne digital channelization device. The implementation method comprises the following steps: designing a prototype low-pass half-band filter; designing a corresponding complementary high-pass half-band filter according to the prototype low-pass half-band filter; taking the prototype low-pass half-band filter up-sampling as an upper branch primary filter, and taking the prototype complementary high-pass half-band filter up-sampling as a lower branch primary filter; designing an upperbranch secondary filter and a lower branch secondary filter and performing multiphase decomposition; signal reconstruction is completed through transposition of multiphase decomposition of upper and lower branch secondary filters. According to the method, the reconstruction error of the original spaceborne digital channelizer is reduced, the guard interval width is reduced, the calculation complexity is reduced, and the method is simple, efficient and easy to implement.

The invention proposes a polyphase decomposition based variable point number fast Fourier transform (FFT) method for a GHz high-speed sampling signal. A conventional FFT processing method is decomposed and the FFT processing of the high-speed sampling signal is decomposed into the processing of a plurality of low-speed signals through a time domain polyphase decomposition technology, so that a possibility is provided for the FFT processing of the high-speed sampling signal; and after the conventional FFT processing method is decomposed into the processing of the low-speed signals in the polyphase manner, low-speed processing results are subjected to weighted synthesis to obtain a final high-speed sampling signal FFT processing result. According to the method, a new polyphase twiddle factor is established, so that the final FFT result is obtained through simple pipelining multiplication and summation operations.

Data samples are filtered by using a digital filter where the length of an impulse response of the digital filter is finite, an impulse response of the digital filter is symmetric and the operation of the digital filter is multi-rate. The method uses a polyphase decomposition to break down the input data stream into N parallel substreams and the multi-rate digital filter is separated by a polyphase decomposition into multiple lower-rate sub-filters where each of the sub-filters is separated into a set of simpler sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.

The invention provides a frame detection method for an orthogonal frequency division multiplexing ultra-wideband system. The method comprises the following steps: performing 1:4 serial-parallel conversion on a received sampling data of an analog-to-digital converter; dividing the data subject to the serial-parallel conversion into two paths; utilizing an optimized matching filter coefficient to perform matching filtering on one path of the data, performing a delaying multiplying operation on a matching filtering result, and then utilizing a weighting coefficient in an exponential form to perform accurate matching filtering on a delaying multiplying result so as to acquire a decision, and finally performing quadruple downsampling treatment on the decision, wherein multiphase decomposition is used for reducing the calculation quantity of weighting accumulation; and estimating the power of the other path of the data to acquire an estimated power value and then performing the quadruple downsampling treatment on the estimated power value, wherein the calculating quantity is reduced since the multiphase decomposition is used for realizing the power estimation and the quadruple downsampling treatment, and a recursive algorithm is used for realizing each multiphase component; and finally, inputting calculated results of the two paths of the data into a comparator, and judging whether a frame exists.

The invention provides a method and a device for digital down converter and filtering extraction, belonging to the field of signal and information processing. The method comprises the following steps: receiving a middle frequency digital signal, and carrying out polyphase decomposition processing with a polyphase decomposition factor of n on the middle frequency digital signal to obtain n paths of signals subjected to the polyphase decomposition processing and output the signals; receiving n paths of signals subjected to the polyphase decomposition processing, carrying out mixed frequency processing on each path of signal subjected to the polyphase decomposition processing to obtain n paths of signals subjected to the mixed frequency processing and output the signals; and receiving n paths of signals subjected to the mixed frequency processing and carrying out filtering extraction processing on the n paths of signals subjected to the mixed frequency processing according to an extraction factor m to obtain n / m paths of digital down converter signals, wherein m, n and n / m are natural numbers which are not equal to zero, and m is more than or equal to n. The device comprises a polyphase decomposition circuit, a mixed frequency circuit and a filtering extraction circuit. The scheme reduces the operation complexity, improves the stability of the processor, and effectively improves the precision and real-time property of the operation at the same time.

The invention provides a high-order multi-phase digital filtering sampling method and system aiming at the problem that hardware cannot be realized due to the fact that the filtering rate of a broadband communication system is too high and the order of a filter is too high. The method comprises the following steps: firstly, carrying out interpolation operation on a digital signal, then carrying out multiphase decomposition on a coefficient of a filter by utilizing symmetry of the filter, then designing a split lookup table by adopting a parallel distribution algorithm, and finally, optimizing the number of stored lookup tables by utilizing symmetry of content of the lookup table. According to the implementation scheme, the storage scale of the lookup table is greatly reduced, resource consumption is reduced, the operation rate and the operation amount are effectively reduced, the working frequency of the filter is greatly improved, and the method is suitable for engineering implementation.

The invention relates to a multi-standard digital filtering implementation method and system, wherein the method comprises the following steps of: identifying data speed according to data frame head; respectively calculating sample point periods of the identified signals with different data speeds, and determining a minimum common sample point period number of each signal; performing multi-phase decomposition on a filter, and completing multiplication-accumulation operation of each phase in clock periods of the minimum common sample point period number. The invention automatically determines the sampling rate by judging the data frame head, without the selection of switch, and reduces the consumption of the clock domain by the using of the same operating clock; furthermore, the data with different bandwidth shares the multiplication-accumulation operation so that the resource consumption is greatly reduced.