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Variable-modulus fractional frequency conversion serial signal processing method and device

A processing method and serial signal technology, applied in the information field, can solve problems such as inability to adapt to frequency conversion requirements, and achieve the effects of simple structure, small processing resources, and high precision

Pending Publication Date: 2020-11-03
36TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Frequency conversion requirements of RF digital receivers that cannot adapt to ADC sampling rate changes

Method used

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  • Variable-modulus fractional frequency conversion serial signal processing method and device
  • Variable-modulus fractional frequency conversion serial signal processing method and device
  • Variable-modulus fractional frequency conversion serial signal processing method and device

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Experimental program
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Embodiment 1

[0049] This embodiment discloses a serial signal processing method with variable modulus and decimal frequency conversion. In the input and output relationship of the rational number decimal frequency conversion, the rational number multiplication decimal conversion process of the interpolation multiple L and the decimation multiple M, where L and M are integers, and the rational number decimation rate is

[0050]

[0051] T 2 Is the output data clock cycle, T 1 Is the input data clock period. In theory, there is a low-pass filter after internal decimation and before decimation. The interpolated filter is used to filter out image spurious, and the pre-decimation filter is used for anti-aliasing. When two filters are cascaded, the frequency response of the equivalent filter h(nT') is equal to the convolution of the two low-pass filters, so it can be represented by one filter. Among them, the frequency response of h(nT’) satisfies

[0052]

[0053] Note that ω above is the normaliz...

Embodiment 2

[0093] This embodiment discloses a serial signal processing device with variable modulus and decimal frequency conversion, such as Image 6 As shown, it includes P one-to-one corresponding RAM blocks, multipliers and data accumulators, and P-1 adders and address generators;

[0094] The P RAM blocks are used to store the filter tap coefficients after polyphase decomposition of the prototype low-pass filter; one RAM block is a memory bank to store M tap coefficients, and the total number of P RAM blocks is N=M ×P tap coefficient of the filter.

[0095] The address generator is used to generate serial output address data and enable signals according to the modulus value M and the interpolation multiple L.

[0096] One multiplier of each multiplier is the data read in serially, and the other multiplier is the tap coefficient extracted from the address data output by the address generator in the corresponding RAM block, and the output terminal of the multiplier is connected to the corres...

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Abstract

The invention relates to a variable-modulus fractional frequency conversion serial signal processing method and device, and the method comprises the steps: determining the order and total tap number of a prototype low-pass filter of a multi-phase filter according to the modulus M and interpolation multiple L of variable-modulus fractional frequency conversion; carrying out multiphase decompositionon the prototype low-pass filter, and grouping and storing tap coefficients into corresponding RAM blocks; generating address data and an enable signal which are output in series under the driving ofa system clock; transmitting address data to an RAM block to take out a tap coefficient, sending the tap coefficient and read-in data to a multiplier for multiplication, sending a multiplication result to a data accumulator corresponding to the RAM block, and under the control of an enable signal, carrying out data accumulation to output an accumulation result; performing cascade addition summation on the output accumulation result, and outputting the result under the control of an enable signal to serve as a final result after frequency conversion. Under the condition of variable-rate blindarea sampling, fixed digital intermediate frequency is obtained through efficient frequency conversion, the structure is simple, processing resources are small, and precision is high.

Description

Technical field [0001] The invention relates to the field of information technology, in particular to a serial signal processing method and device with variable modulus and decimal frequency conversion. Background technique [0002] When the Nyquist bandwidth of the ADC is smaller than the frequency range of the receiver, variable rate blind zone sampling is required to make up for the sampling blind zone introduced by a single sampling frequency. For this reason, it is necessary to introduce efficient multi-rate signal processing technology. In the past, many application scenarios involved in multi-rate digital signal processing were the process of down-conversion through integer multiples or decimal multiples decimation under the premise that the sampling rate of the ADC remains unchanged. For example, for existing high-speed ADCs, regardless of ADI or TI, the embedded broadband digital down-conversion assumes a fixed sampling rate and extracts integer multiples or decimals to...

Claims

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Application Information

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IPC IPC(8): H03M1/12
CPCH03M1/124Y02D10/00
Inventor 陈顺阳朱梦磊徐力张琦杨会宇
Owner 36TH RES INST OF CETC
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