An analog signal processor, accessing to a setting register through serial communication, for achieving high speed of selective bit setting therein, comprising: an address register 3, a data register 4, a mask register 5, and a AND-OR logic circuit 6, wherein address data “a”, setting data “d” and mask data “m” are transmitted through serial communication. Reading out a register designated by the address data “a” and conducting AND operation on the mask data “m” for each bit thereof, and further conducting OR operation upon the setting data “d” for each bit thereof, a result obtained thereby is written back into a register 8 designated by the address data. When no mask data portion is transmitted, the same process is conducted, assuming that it is the mask data of all bits being zero.