Memory system and method of operating the same

Abstract

A method of operating a memory system includes classifying numbers of total error bits into a plurality of ranges, assigning a plurality of data to the plurality of ranges, respectively, counting a number of detected error bits for a memory cell block, and storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2010-0139185 filed on Dec. 30, 2010, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments relate to a memory system and an operating method thereof, and more particularly, to a memory system that classifies memory cell blocks according to the number of erroneous bits and an operating method thereof. Background technique [0004] After the semiconductor memory device is manufactured, a test operation for judging whether a memory cell block of the semiconductor memory device belongs to a normal block or an unusable bad block is performed. The test operation can be performed in various ways, one of which is to perform a test program operation or a test erase operation using test data. This method will be described below. [0005] figure 1 is a diagram illustrating a memory cell array. [...

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Problems solved by technology

[0009] Error correction operations cannot be applied to memory cell blocks with a large number of erroneous bits

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