Carry-saving multiplier

A multiplier and carry-out technology, applied in the field of carry-save multipliers, can solve problems such as irregularity and high-quality layout design difficulties, and achieve the effects of regular structure, reduced multiplier area, and improved speed and power consumption

Inactive Publication Date: 2012-10-10
PEKING UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] In the design of large-scale integrated circuits, although the tree structure multiplier has the a...

Method used

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Embodiment Construction

[0055] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0056] The present invention will be described in detail below in combination with the design idea of ​​the invention.

[0057] From figure 2 The traditional carry-save multiplier shown can be analyzed, and the input signals of each adder therein are not completely independent, and some signals may have common factors, and the simplification of the carry-save multiplier by the present invention starts from this point . Through analysis, it can be found that there are two full adders ( figure 2 marked as FA1 and FA2) are quite special. Its particularity lies in the certain correlation between their 3 input signals. The following is a simple analysis of the two respec...

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Abstract

The invention discloses a carry-saving multiplier, relating to the technical field of integrated circuit. Through analysis on the conventional carry-saving multiplier, full adders at two special positions in an array can be logically simplified, so that the speed and the power consumption are optimized on the premise of reducing the area of the multiplier; and furthermore, in an AND gate array for generating a partial product, each row of AND gates has a common signal, so that the number of transistors is reduced by sharing a downwardly drawn NMOS (N-channel Mental-oxide-semiconductor) tube; therefore, in combination of the two ways, a novel simplified carry-saving multiplier is constructed. A simulating result shows that compared with the conventional carry-saving multiplier, the carry-saving multiplier disclosed by the invention can reduce a power consumption delay product as high as 12.41 percent; the improved carry-saving multiplier still has the advantage of structural regularity of all array multiplier, so that the improved carry-saving multiplier is still applicable to design of a large-scale integrated circuit; and meanwhile, due to advantages in the speed and the power consumption of the improved carry-saving multiplier, performance of a circuit system can be further improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a carry-save multiplier. Background technique [0002] Multiplication [1] is the most basic and important operation in digital signal processing. The speed and power consumption of the multiplier will largely determine the performance of the entire circuit system. A multiplier generally consists of three parts: partial product generation, partial product compression, and a final adder chain [2]. Partial products can be generated directly through an AND gate array, or can be generated through a special algorithm (such as the improved booth algorithm [3]). The compression of partial products can be a regular adder array, or a special tree structure (such as a wallace tree [4]). The final adder chain can directly use the chain ripple carry structure when the scale of the multiplier is small, and other high-speed carry chain structures (such as the carry selection adde...

Claims

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Application Information

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IPC IPC(8): G06F7/52
Inventor 贾嵩李夏禹刘俐敏
Owner PEKING UNIV
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