VLSI (Very Large Scale Integration) circuit integrating method

Abstract

The invention particularly relates to a VLSI (Very Large Scale Integration) circuit integrating method. The VLSI circuit integrating method is that the down-top integrating strategy is utilized; when each sub-module at the bottom level is integrated, the module at the previous level is integrated until reaching the top level of a chip; a special script is combined with the general script, and Error / report extraction script is also provided; each setting script is unified to be managed through the created executable script, rather than being directly written into a DC platform; the executable script is read to sequentially transfer each setting script. According to the VLSI circuit integrating method, the down-top strategy is utilized for integrating the VLSI circuit; the scripts are controlled, an integrating platform is divided into special settings and general settings, and therefore, the integrating platform can be simply and conveniently maintained; in addition, the setting scripts are extracted for the added information, so that the log files and integrating results can be automatically processed.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a VLSI synthesis method for very large scale integrated circuits. Background technique [0002] With the continuous development of digital integrated circuits, the complexity of the chip is getting deeper and deeper, and the scale is getting bigger and bigger. The synthesis work is an important bridge to communicate the front-end logic design and the back-end physical design. The speed and quality of the synthesis work seriously affect the development of the back-end physical design, which has an important impact on the tape-out of the chip. Therefore, it is necessary to build a reasonable and efficient comprehensive environment to speed up the comprehensive work. For VLSI, there are two important problems in the synthesis process: one is that there are many layers of chip logic, and each layer contains several sub-modules; the other is that the scale is large,...

AI Technical Summary

Problems solved by technology

For VLSI, there are two important problems in the synthesis process: one is that the chip has many logic layers, and each layer contains several sub-modules; the other is that the scale is large, possibly hundreds of millions of circuits.

If the full-chip synthesis is performed, a large amount of memory is required, which puts high demands on the server. At the same time, it takes a long time, and various settings cannot be corrected in time, which seriously affects the quality and quantity of the netlist submission.

[0003] Very large-scale integrated circuits, the scale is too large, and the overall chip synthesis usually adopts a top-down top-down strategy. This synthesis method has problems such as high resource requirements, large time overhead, and high iteration costs. At the same time, there are many chip levels and module differentiation, which cannot be adopted. Synthesize and optimize timing with the exact same synthesis constraints

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