Frequency domain implementation method of high-speed high-order FIR filter used for FPGA

An implementation method and filter technology, applied in the direction of impedance network, digital technology network, electrical components, etc., can solve the problem of FPGA resource consumption and processing speed, and achieve the elimination of zero padding delay phenomenon, solve resource consumption, and improve processing speed effect

CN104967428AActive Publication Date: 2015-10-07NANJING UNIV OF INFORMATION SCI & TECH
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2015-10-07

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Abstract

The invention discloses a frequency domain implementation method of a high-speed high-order FIR filter used for FPGA. When convolution operation is processed by utilization of a frequency domain, the problem that data cannot be processed in real time caused by zero filing time consumption is solved, an original conventional scheme of processing a sequence by utilization of one FFT IP is changed to a scheme of operating inputted data by utilization of two FFT IPs. Two FFTs output sectional convolution data respectively, and the difference of the later convolution and the previous convolution is just N clocks. Because the length of the sectional convolution is 2N, the previous N data and the previous sectional convolution are added, and the later N data and the later sectional convolution are added. Thus superfluous time-delay is not needed during overlap addition, a convolution result can be obtained, and therefore signal in-real processing is achieved. The provided frequency domain implementation method can lower FPGA resource consumption, can eliminate zero filling delay phenomena in the prior art, raises the processing speed, and can achieve real-time processing.
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Description

technical field

[0001] The invention relates to the technical field of discrete signal processing, in particular to a frequency-domain implementation method of a high-speed high-order FIR filter for FPGA. Background technique

[0002] In digital signal processing system, FIR (Finite Impulse Response) filter is the most basic unit. Due to its strict linear phase-frequency characteristics and stable system, FIR has become the main means of data processing in many fields. With the development of electronic technology, the signal sampling frequency is constantly increasing. Under high-speed sampling, the FIR filter based on the multiplier structure and the FIR filter based on the distributed algorithm can perform fast pipeline real-time processing in the FPGA, but like pulse The compression technology is similar to the FIR filter, and its order is tens of thousands, which consumes too much FPGA resources.

[0003] The Fast Fourier Transform (FFT) is a method that can implement...

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Embodiment Construction

[0035] In order to make the object, technical solution and advantages of the present invention clearer, the real-time solution of the present invention will be further described in detail below in conjunction with embodiments and drawings.

[0036] The invention provides a method for implementing a high-speed high-order FIR filter in the FPGA in the frequency domain. The method improves the problem that the data cannot be processed in real time due to time-consuming zero padding when the convolution operation is processed in the frequency domain. , changing the conventional scheme of using one FFTIP to process the sequence to use two FFTIPs to operate on the input data, the sequence timing is as follows image 3 shown. This method is suitable for systems whose coefficients are real or complex integers, for very high-order systems, for pulse compression systems, and for systems with configurable coefficients.

[0037] The technical solution of the present invention will be des...