Semiconductor package and manufacture method thereof

Abstract

The invention provides a semiconductor package and a manufacture method thereof. The semiconductor package comprises a board body, semiconductor wafers and packaging colloid members. Each semiconductor wafer is provided with an action surface and a non-action surface which face each other. Furthermore the non-action surface contacts with the board body. The packaging colloid members package the board body and the semiconductor wafer and respectively comprise a first surface and a second surface which face each other. The first surfaces are exposed from the action surfaces of the semiconductor wafers. The semiconductor package and the manufacture method thereof have an advantage of effectively improving structure strength for preventing warpage of the semiconductor package.

Description

technical field [0001] The invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package embedded with a board body and its manufacturing method. Background technique [0002] With the evolution of semiconductor technology, different packaging product types of semiconductor products have been developed. In order to pursue the lightness, thinness and shortness of semiconductor packages, a Chip Scale Package (CSP) has been developed, which is characterized in that the chip Size packages are only of equal or slightly larger size than the die size. [0003] Figure 1A to Figure 1D What is shown is a cross-sectional view of a manufacturing method of a conventional semiconductor package. [0004] like Figure 1A As shown, a first carrier board 10 is provided, and a release layer 11 and a first adhesive layer 12 are sequentially formed thereon. [0005] like Figure 1B As shown, a plurality of semiconductor wafers 13 with op...

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Problems solved by technology

[0009] However, in the above-mentioned manufacturing process of the conventional semiconductor package, after the curing step of the encapsulant, the difference between the thermal expansion coefficient of the encapsulant and the thermal expansion coefficient of the first carrier board is too large, so warpage (warpage) will occur (such as Figure 1D shown), therefore the second carrier board must be additionally attached to balance the stress and reduce the degree of warpage, and then the circuit redistribution layer can be formed on the active surface of the semiconductor chip and the first surface of the encapsulant. However, this will Increase overall process cost and time

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