Multi-core parallel video decoding method for allocating tasks and data by row in staggered manner

A line-by-line interleaving and video decoding technology, applied in the field of video coding, to achieve the effect of improving access efficiency

Active Publication Date: 2016-03-02
广东世寰智能科技有限公司
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  • Claims
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Problems solved by technology

Specific measures need to find out the problems of the third method in the literature

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  • Multi-core parallel video decoding method for allocating tasks and data by row in staggered manner
  • Multi-core parallel video decoding method for allocating tasks and data by row in staggered manner
  • Multi-core parallel video decoding method for allocating tasks and data by row in staggered manner

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Embodiment Construction

[0064] The embodiment of the present invention is 1080P@30Hz H.264 video decoding on Tile64. Refer below Figure 1-9 Describe in detail.

[0065] The H.264 decoding software used in the present invention is derived from JVT official reference codec software JM6.1e. Before the implementation of the present invention, simplification and optimization have been carried out according to the application requirements of video conferencing. Among them, the most meaningful modification to the present invention is to expand the structure and storage capacity of syntax symbols in the JM6.1e decoding software from one macroblock to one frame of image, and change the code stream analysis and image reconstruction processed by macroblock to be completed first. One frame of image code stream analysis is completed and then one frame of image reconstruction is completed, and finally the deblocking loop filtering of one frame of image is completed. This is the basis and starting point for org...

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Abstract

The invention provides a multi-core parallel video decoding method for allocating tasks and data by row in a staggered manner. Shared image data is allocated and processed according to the following steps: (11) image data of an HxW image and processing tasks thereof are allocated to m cores by code stream basic unit row in a staggered manner, wherein the 0th row is allocated to the core 0, the 1st row is allocated to the core 1, the 2nd row is allocated to the core 2,..., the core i processes the ith, (i+m)th, (i+2*m)th,..., (i+q*m)th (i+q*m<H / 16k-1) rows of code stream basic units, each core processes video decoding of an hxW sub image, and h=[H / m+0,5]; and (12) after allocation, the mapping relationship from the global row coordinates of the complete image to the core number and the local row coordinates of the sub images thereof is as follows: the image Y component row coordinate mapping is global_y=core number*16k+local_y*m, the image U and V component row coordinate mapping is global_y=core number*8k+local_y*m, the code stream basic unit row coordinate mapping is global_mb_y=core number+local_mb_y *m. After the tasks are allocated to the multiple cores, data caches are correspondingly allocated to the multiple cores, and equilibrium is achieved for all. The shared data access efficiency and the parallel speed-up ratio are significantly improved.

Description

technical field [0001] The present invention relates to the technical field of video coding, in particular to a multi-core parallel video decoding method using a multi-core digital signal processor DSP chip to complete high-definition video encoding, decoding and transmission, as well as optimization measures for load sharing, execution waiting and blocking, and cache memory during multi-core parallelism. Background technique [0002] In the 1980s, the mutual penetration and integration of 3C (Computers, Communications, Consumer Electronics) gave birth to multimedia technology and promoted the rapid development and popularization of multimedia technology. Video coding is a key technology in multimedia technology. In recent years, the clarity of transmitted video has been continuously improved, and at the same time, video coding standards have been frequently updated, and new content has continued to emerge. In 2002, CIFH.263 still occupied the mainstream in conference TV eq...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/436H04N19/44H04N19/82
Inventor 宋立锋杜永红郭俊兵刘诏书
Owner 广东世寰智能科技有限公司
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