A Fast Clock Synchronization Method for Ethercat Master Station Control System

A master station control and clock synchronization technology, applied in transmission systems, time division multiplexing systems, electrical components, etc., can solve the problems of EtherCAT master station and reference clock packet loss, slow clock synchronization speed, etc., to avoid time loss , to avoid the problem of packet loss and ensure the effect of stable operation

Active Publication Date: 2019-01-15
SOUTH CHINA UNIV OF TECH
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Problems solved by technology

[0003] The purpose of the present invention is to overcome the problem of packet loss caused by the asynchrony between the EtherCAT master station and the reference clock in the prior art and the slow synchronization speed of clocks such as PI controllers, and provide a EtherCAT master based on clock frequency follow-up. Fast Clock Synchronization Method for Station Control System

Method used

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  • A Fast Clock Synchronization Method for Ethercat Master Station Control System
  • A Fast Clock Synchronization Method for Ethercat Master Station Control System
  • A Fast Clock Synchronization Method for Ethercat Master Station Control System

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Embodiment

[0035] Please see attached figure 1 , with figure 1 is a flowchart of the fast clock synchronization method for the EtherCAT master control system. The present invention adopts the RTX real-time kernel based on Windows to realize the EtherCAT master station. In the RTX system, the operating frequency of the clock cannot be changed, and the present invention adopts a relative clock synchronization method to realize the synchronization between the EtherCAT master station and the reference clock. Although the RTX real-time kernel can reach the clock synchronization accuracy of 1us, but under the premise of not affecting the system performance, CLOCK2 is selected, and the minimum resolution is 10us. The specific process is as follows:

[0036] Step S1, respectively setting a fixed-period timing thread and a variable-period timing thread, the fixed-period timing thread transmits and processes information for configuring communication channels and performing data interaction with...

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Abstract

The invention discloses a quick clock synchronization method for an EtherCAT master station control system. The quick clock synchronization method includes the steps: realizing quick clock synchronization by means of a clock frequency following method; setting a fixed period timing thread and a changeable period timing thread, and respectively processing the aperiodic data and the periodic data; and completing the clock frequency following function by changing the period of the changeable period timing thread. The quick clock synchronization method realizes synchronization of an EtherCAT master station and a reference clock, and can avoid the packet loss problem caused by clock asynchronization. The quick clock synchronization method utilizes the frequency following method to realize quick clock synchronization, avoids the influence of overlarge overshoot and uncertainty of settling time in the other clock synchronization methods on system performance, and can accurately and quickly track the operation frequency of the reference clock. The quick clock synchronization method utilizes the method of changing the operation frequency of the master station clock to realize clock synchronization, avoids time loss caused replacement of moment, and can guarantee stable operation of the system.

Description

technical field [0001] The invention relates to the field of industrial automation, in particular to a fast clock synchronization method for an EtherCAT master station control system. Background technique [0002] In a distributed motion control system, clock synchronization is the basis for ensuring the coordination between the controller and each execution end, and between each execution end. EtherCAT adopts the principle of distributed clock to keep the clock of each slave station synchronized with the reference clock (usually the first EtherCAT slave station supporting the distributed clock function in the logical ring topology), and the synchronization accuracy can reach 1us. However, the clock synchronization function of the EtherCAT distributed clock is realized by a dedicated hardware logic module, and the method is not applicable to the EtherCAT master station implemented on the PC. At the same time, in the field of motion control that requires high speed, precisio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L29/08H04J3/06
CPCH04J3/0638H04J3/0661H04L67/10
Inventor 李迪陈鑫王世勇
Owner SOUTH CHINA UNIV OF TECH
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