A bit stream file parsing method and timing refresh method based on virtex5 device

Abstract

The invention discloses Virtext5 device-based bit stream file analysis method and a timed refreshing method. The analysis method comprises the following steps of: (1) carrying out bottom architectureanalysis on at least 8 series of Virtext5-type devices and determining a resource type of each series of devices; (2) analyzing bit stream file frame structures of each series of devices, determininga bit number of each frame and a resource type, a size and a position included in each frame, and calculating a total bit number of the bit stream files; (3) generating bit stream files of corresponding series of Virtext5-type devices through ISE according to results of the steps (1) and (2), comparing a total bit number of the generated bit stream files with the total bit number calculated in thestep (2), judging whether analysis of the step (1) and (2) is correct or not, if the judging result is positive, executing step (4), and otherwise, carrying out analysis again from the step (1); and(4) aiming at each series of devices, constructing multi-element equations, the resource types and lengths of which are unknown according to the total bit number of the bit stream files so as to obtain a multi-element equation set, and solving the equation set to obtain sizes of the resource types.

Description

technical field [0001] The invention belongs to refresh reconstruction technology. Background technique [0002] The space radiation environment will cause single event flipping problems in SRAM-type FPGAs, and its severity may cause failures such as "abnormality", "disorder" or "crash" of system programs, reducing the reliability of on-board digital processing equipment. The reinforcement of FPGA mainly relies on timing refresh, and the core of refresh is the extraction of BRAM resources in the bit stream file. Through the extraction, the configuration file is reframed, and the refresh is realized according to a certain configuration sequence. Device manufacturers no longer provide Virtex5 and above devices. related information. [0003] The literature "Research on a Highly Reliable FPGA Design Architecture for Aerospace Applications", after analyzing the shortcomings of the previous SRAM FPGA system design, this paper proposes a three-mode redundant architecture (TMR) and...

AI Technical Summary

Problems solved by technology

The above two patents are all refresh technology research for Virtex2 devices. Xilinx provides Virtex2 related refresh materials. After Virtex5, Xilinx no longer provides any related refresh materials. Compared with Virtex2, Virtex5 has device resource types, frame structures, and configurations. The size of the files has changed greatly, and there is no way to know the resource size of the BRAM, so there are certain differences

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