Interrupt operation method for PCIe controller of adapter card of TTE terminal system

Abstract

The invention discloses an interrupt operation method for a PCIe controller of an adapter card of a TTE terminal system, and aims to solve the problem of overflow loss of data due to insufficient cache space of the adapter card caused by the fact that a host initiates a read interrupt in the prior art. According to the technical scheme, the method comprises the steps of 1) requesting for read or write data; 2) periodically requesting for the read or write data to the PCIe bus controller; 3) generating an interrupt time sequence and configuring a read or write cache register by the PCIe bus controller; 4) identifying an interrupt type and determining a data migration amount by a PCIe driver; and 5) configuring read or write related registers and starting a direct memory access operation tocomplete data migration by the PCIe driver, and finishing the direct memory access operation. According to the method, the direct memory access read or write operation is initiated through the adaptercard; the flow control is realized; the adapter card is used for actively sending out the interrupt, so that the time precision of the terminal system is improved; and the method can be used for design of a time-triggered interrupt module in the adapter card of the Ethernet TTE terminal system.

Description

technical field [0001] The invention belongs to the technical field of communication, and in particular relates to an interrupt operation method of a PCIe controller interconnected with high-speed peripheral components, which can be used to time-trigger the design of an interrupt module in an adapter card of an Ethernet TTE end system, so as to ensure that data will not be buffered by the adapter card Area overflow and loss, and improve the time precision of the time-triggered Ethernet TTE end system. Background technique [0002] High-speed peripheral component interconnect PCIe is a high-speed serial transmission bus with point-to-point, dual-channel and high-bandwidth transmission characteristics. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. After the direct memory access DMA operation on the side of the board is completed, a read / write interrupt is generated through the PCIe bus controller to inform the board on the host...

AI Technical Summary

Problems solved by technology

[0004] First, after the host fills in the direct memory access DMA read and write related registers, when the board is moving data, the data will be lost due to the buffer overflow of the board, and flow control cannot be realized;

[0005] Second, the host, as the active party, fills in the direct memory access DMA to read and write related registers, and actively initiates data transmission operations. Due to the influence of the host operating system, its time accuracy is far inferior to that of the board card actively initiating data transmission operations.

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