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Method and device for compressing redundant information in fault-tolerant NVM persistence process

A technology of redundant information and compression method, applied in the input/output process of data processing, instruments, electrical digital data processing and other directions, can solve the problems of long NVM delay, no processing, etc., achieve low overhead, simple compression method, improve The effect of persistence efficiency

Active Publication Date: 2019-03-29
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

from figure 2 As can be seen in the above, no matter what kind of log mechanism, there is a certain overhead in persistence: two write operations (write to the log and write to the persistent heap) must be performed, and each write operation requires data update ( Flush) and operation synchronization (fence) are two time-consuming operations to ensure that the write persistence is completed, and the NVM write operation itself has a long delay
On the other hand, such log persistence only simply writes the address and value information into NVM, and does not deal with the redundancy of information locality during program execution.

Method used

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  • Method and device for compressing redundant information in fault-tolerant NVM persistence process
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  • Method and device for compressing redundant information in fault-tolerant NVM persistence process

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Embodiment Construction

[0045] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other. The log mechanism in this embodiment is a redo log (that is, record new values).

[0046] like image 3 As shown, the implementation steps of the method for compressing redundant information of the fault-tolerant NVM persistence process in this embodiment include:

[0047] 1) Allocate the write set WriteSet, address queue queue and multiple value queues vqueue_X in the thread that supports trans...

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Abstract

The invention discloses a method and a device for compressing redundant information in a fault-tolerant NVM persistence process. The implementing steps of the invention include allocating a write set,an address queue and a plurality of value queues, and allocating a persistence log storage area in the NVM. Writing all persistent write operation information to the write collection during the transaction; Scaning the write set, adding the corresponding value queue according to the new and old comparison of the values, and adding the address queue according to the value queue in order; compressing The address information in the address queue so that the same part of a group of adjacent addresses is eliminated, and writing the compressed address information into the address record. Wirtting The lower X bits of the N-bit values of all elements in the individual value queues to the value record, thereby eliminating redundant information of the values. The invention can reduce the size of the persistent data, thereby reducing the persistent overhead of the transaction, achieving the purpose of improving the persistent transaction performance and prolonging the service life of the NVM.

Description

technical field [0001] The present invention relates to the field of computer persistent memory, in particular to a method and device for compressing redundant information in a fault-tolerant NVM persistent process, which is used to compress redundant information in persistent storage to improve the write performance and lifespan of persistent memory . Background technique [0002] In recent years, with the rapid development of the computer field, the processing capacity of the central processing unit CPU has been greatly improved, while the performance improvement of the storage system is relatively small. There is a huge performance gap between the traditional main memory-auxiliary memory structure. It has become the performance bottleneck of the computer system. [0003] On the one hand, in the traditional main memory-auxiliary memory system, the main memory (usually DRAM, Dynamic Random Access Memory, dynamic random access memory) usually has the characteristics of smal...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
CPCG06F3/0608G06F3/0616G06F3/0638G06F3/0679
Inventor 彭林张文喆陈俊峰黄春唐滔方建滨左克姜浩
Owner NAT UNIV OF DEFENSE TECH
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