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Acceleration library design method, terminal equipment and storage medium

A design method and acceleration library technology, applied in the computer field, can solve problems such as the inability to support DSP optimization

Active Publication Date: 2019-11-22
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of this, the embodiment of the present invention provides an acceleration library design method, a terminal device and a storage medium to solve the problem that all existing forward reasoning engines in the prior art cannot support DSP optimization

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  • Acceleration library design method, terminal equipment and storage medium
  • Acceleration library design method, terminal equipment and storage medium
  • Acceleration library design method, terminal equipment and storage medium

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Embodiment Construction

[0022] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0023] At present, all existing forward reasoning engines only support ARM optimization and cannot support DSP optimization. The CNN forward reasoning engine acceleration library based on the CEVA DSP chip of the present invention can be transplanted to the existing forward reasoning engine, so that the existing forward reasoning engine supports DSP optimization, and supports the development of ne...

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Abstract

The invention is suitable for the technical field of computers, and provides an acceleration library design method, terminal equipment and a storage medium, and the method comprises the steps: carrying out the fixed-point processing of the data of a CNN (Convolutional Neural Network) model, and employing integer data to represent the floating point type data of the CNN model; loading hidden layerdata corresponding to a hidden layer of the CNN model into an internal memory IDM through a disk direct memory access DDMA optimization scheme; and according to the hidden layer data loaded into the IDM, calculating the hidden layer data through a vector processing unit VPU of the CEVA DSP chip so as to optimize the CNN model. The acceleration library is optimized through the DDMA technology and the VPU instruction, most operation of the CNN model is supported, the acceleration library can be transplanted into an existing forward reasoning engine, the existing forward reasoning engine supportsDSP optimization, and a new forward reasoning framework is developed on the basis of the acceleration library.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a design method of an acceleration library, a terminal device and a storage medium. Background technique [0002] At present, with the continuous improvement of large-scale convolutional neural network (Convolution Neutral Network, CNN) network hardware requirements, CNN forward reasoning engines have emerged, such as NCNN developed by Tencent, MNN developed by Alibaba and Nvidia. TensorRT developed by the company. According to statistics, on a global scale, one out of every three smartphones uses CEVA DSP technology, and all existing forward reasoning engines only support ARM optimization and cannot support DSP optimization. Therefore, it is difficult for terminals using CEVA DSP technology to use the existing forward reasoning engine for intelligent image and visual processing, which is not conducive to the wide application of the forward reasoning engine. Cont...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/063G06F16/21
CPCG06N3/063G06F16/212G06N3/045
Inventor 张洪光
Owner TP-LINK
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