Semiconductor package structure and manufacturing method of semiconductor package
A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., to avoid warpage, improve stability, and avoid cracking
Active Publication Date: 2020-05-15
亿芯微半导体科技(深圳)有限公司
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Problems solved by technology
The packaging process is: the wafer from the wafer front-end process is cut into small chips after the dicing process, and then the cut chips are glued to the corresponding substrate, and then ultra-fine metal wires or conductive Connect the bonding pads of the chip to the corresponding pins of the substrate with a flexible resin to form the required circuit; then package and protect the independent chip with a plastic shell, and then perform a series of operations after the package is completed. Testing, usually after inspection, testing, packaging and other processes, and finally warehousing and shipment. However, the stability and durability of existing semiconductor packages have attracted more and more attention. How to optimize the manufacturing process of semiconductor packages , is a problem to be solved in the industry
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[0023] The present invention proposes a method for manufacturing a semiconductor package, comprising the following steps:
[0024] 1) A carrier substrate is provided, and a bonding layer is formed on the upper surface of the carrier substrate. The material of the carrier substrate is one of silicon, glass, ceramics, and a resin plate, and the bonding layer is The viscosity is lost, which in turn can facilitate the dissociation of the carrier substrate.
[0025] 2) Next, a first passivation layer is formed on the upper surface of the carrier substrate, the material of the first passivation layer is one or more of alumina, silicon oxide, and zirconia, and the first passivation layer is The manufacturing method of the layer is ALD or PECVD, and the thickness of the first passivation layer is 300-800 nanometers. In a specific embodiment, the first passivation layer is an aluminum oxide layer, which is deposited and formed by ALD method, The thickness of the first passivation laye...
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Abstract
The invention relates to a semiconductor packaging structure and a manufacturing method thereof, and the method comprises the following steps: providing a bearing substrate, and forming a bonding layer on the upper surface of the bearing substrate; forming a first passivation layer on the upper surface of the bearing substrate; forming a first dielectric layer, a first metal circuit layer, a second dielectric layer, a second metal circuit layer, a third dielectric layer and a second passivation layer on the first passivation layer; forming a solder column on the exposed second metal circuit layer, mounting a semiconductor chip on the solder column, and irradiating the solder column by using a second laser to form a plurality of micro concave holes in the surface of the solder column; and forming a molding compound, removing the bonding layer and the bearing substrate, forming a solder mask layer on the exposed surface of the first passivation layer, forming a second opening in the first passivation layer and the solder mask layer, and forming a solder ball in the second opening.
Description
technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging structure and a semiconductor packaging manufacturing method. Background technique [0002] Semiconductor packaging refers to the process of processing the tested wafers according to the product model and functional requirements to obtain independent chips. The packaging process is: the wafer from the wafer front-end process is cut into small chips after the dicing process, and then the cut chips are glued to the corresponding substrate, and then ultra-fine metal wires or conductive Connect the bonding pads of the chip to the corresponding pins of the substrate with a flexible resin to form the required circuit; then package and protect the independent chip with a plastic shell, and then perform a series of operations after the package is completed. Testing, usually after inspection, testing, packaging and other processes, and finally warehousing ...
Claims
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IPC IPC(8): H01L21/50H01L21/56H01L21/60H01L23/31
CPCH01L21/50H01L21/568H01L23/3107H01L24/81H01L2224/81815H01L2224/81939H01L2224/16225H01L2924/15311H01L2924/181H01L2924/00012
Inventor张正
Owner亿芯微半导体科技(深圳)有限公司