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Interrupt processing system and method applied to PCIE to heterogeneous equipment

A processing system and processing method technology, applied in the field of PCIE interrupt processing system for heterogeneous devices, can solve problems such as costing development costs, achieve the effect of reducing verification costs and improving interrupt processing efficiency

Pending Publication Date: 2021-01-19
KUNSHAN SHANGNISI ELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, for the supplier, every revision needs to verify the driver, and the verification program is a large amount of development cost.

Method used

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  • Interrupt processing system and method applied to PCIE to heterogeneous equipment
  • Interrupt processing system and method applied to PCIE to heterogeneous equipment
  • Interrupt processing system and method applied to PCIE to heterogeneous equipment

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Embodiment Construction

[0019] Please refer to the accompanying drawings and examples to describe the implementation of this application in detail, so as to fully understand and implement the implementation process of how to apply technical means to solve technical problems and achieve technical effects in this application.

[0020] Please refer to Figure 1, which is a schematic diagram of the system architecture of this application. The interrupt processing system 100 of the present application can be applied to a personal computer, a notebook computer or an embedded computer having a PCIE pin 133 . The PCIE interrupt processing system 100 for heterogeneous devices of the present application includes a processing unit 110 , a storage unit 120 and a PCIE adapter card 130 . The processing unit 110 is electrically connected to the storage unit 120 and the PCIE riser card 130 . The heterogeneous device referred to in this application refers to the PCIE pin-based device, compared to other types of commu...

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Abstract

The invention discloses an interrupt processing system and method applied to PCIE to heterogeneous equipment. The interrupt processing system comprises a PCIE adapter card, a storage unit and a processing unit. Wherein the PCIE riser card is provided with a control unit, identification information and at least one communication interface, and the control unit is electrically connected to the communication interfaces; wherein the storage unit is provided with a service program, a drive program and a plurality of cache structures, and each cache structure is used for storing interrupt requirements; the processing unit is electrically connected to the PCIE riser card and the storage unit, the processing unit executes a driving program and a service program, the driving program establishes a plurality of transmission channels according to the identification information, the driving program assigns corresponding communication interfaces to different transmission channels, and the transmission channels are used for transmitting interrupt requirements or access requirements; and if the drive program detects the transmission interruption requirement of any transmission channel, the drive program stores the interruption requirement into the cache structure, and if the interruption requirement exists in the cache structure, the service program processes the interruption requirement.

Description

technical field [0001] A system and method for interrupt processing of peripheral hardware resources, especially related to the interrupt processing system and method applied to PCIE for heterogeneous devices Background technique [0002] Although various low-speed communication interfaces (for example: Digital I / O, Analog I / O or RS-232, etc.) that are traditionally used can be transferred to other high-speed communication interfaces (for example: Universal Serial Bus (Universal SerialBus, USB) or Peripheral Component Interconnect Express (PCIE for short). However, the Interrupt Service Routine (ISR) that is limited by the traditional communication interface will affect the transmission efficiency of the high-speed transmission interface. [0003] Because the traditional communication adopts the polling mechanism, the controller will ask the connected terminal equipment one by one whether there is an interrupt request. When a terminal device sends an interrupt request, the...

Claims

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Application Information

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IPC IPC(8): G06F13/22G06F13/40
CPCG06F13/225G06F13/4022G06F2213/0026
Inventor 林忠杰
Owner KUNSHAN SHANGNISI ELECTRONICS TECH CO LTD
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