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Bus checking method and device

A bus inspection and bus technology, applied in the field of communication, can solve the problems of omission, manual review time-consuming and laborious, etc., to achieve the effect of improving accuracy, saving R&D cycle and labor input cost, and avoiding uncertainty

Pending Publication Date: 2022-05-13
NEW H3C TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, this review work is done manually. For a large schematic diagram, there may be many bus types at the same time, and the number of all buses may add up to hundreds. Manual review is time-consuming and laborious, and there may be omissions

Method used

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  • Bus checking method and device

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Embodiment Construction

[0044] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application.

[0045] The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and al...

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Abstract

The invention provides a bus checking method and device. The method comprises the following steps: determining a target chip to be examined in a single board according to a device list of the single board; according to pre-stored chip attribute information of chips in the single board, if it is confirmed that a bus needing to be examined exists in the target chip, pins of the existing bus are extracted from the chip attribute information of the target chip; according to the netlist of the single board, performing network series connection on pins corresponding to the extracted pin information of the bus to obtain a pin network; checking the pin network, and judging whether the pin network has pins with different attributes or not; and when the pins with different attributes exist in the pin network, determining that the target chip has a bus reverse connection condition. Therefore, the automatic checking of the bus is realized, the labor cost is saved, and the accuracy of the checking result is improved.

Description

technical field [0001] The present application relates to the technical field of communications, and in particular to a bus inspection method and device. Background technique [0002] Various types of buses are used in circuit design, including data buses, clock buses, etc., for communication between chips and modules. There are many types of buses, such as serial bus, parallel bus, single-ended bus, differential bus and so on. And no matter what kind of bus, it must follow the requirements of the same attribute docking in application. For example, the bus between two chips and modules must be clock-clock docking, data-data docking, positive (P) and positive (P) docking , the negative pole (N) is docked with the negative pole (N), if there is a reverse connection, the bus communication will fail. Therefore, when reviewing the schematic design, it is necessary to check whether there is a reverse connection of the bus to ensure the correctness of the circuit design. [0003...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F13/42
CPCG06F30/398G06F13/4282G06F2213/0016
Inventor 闫宗尧覃远松
Owner NEW H3C TECH CO LTD
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