Apparatus for controlling color liquid crystal display and method thereof

Abstract

An apparatus for controlling a color liquid crystal display and method thereof are disclosed, by which data transfer efficiency is raised in a manner of changing an input interface type of an LCD controller, by which a same-sized video can be outputted with a smaller number of clocks, and by which practical applicability of CPU is enhanced. The present invention includes a clock control unit providing a clock for operating each module, an interface unit receiving 16-bit data each clock according to a control signal of the clock control unit, a pair of 18-bit RGB buffers storing data transferred via the interface unit, a graphic buffer storing graphic data provided from a pair of the RGB buffers, a switching block storing data signals provided from a pair of the RGB buffers in the graphic buffer, and a digital / analog converting unit converting digital R / G / B data stored in the graphic buffer to an analog signal to output.

Description

[0001] This application has the benefit of Korean Patent Application No. 10-2004-0071328 filed on Sep. 7, 2004, which is hereby incorporated by reference for full disclosure herein. (1) Technical field [0002] The invention relates to a color liquid crystal display, in particular to a device and method for controlling the color liquid crystal display. Although the invention is applicable to a wide range of applications, it is particularly suitable for reducing the processing time of a central processing unit with a 16-bit interface. (2) Background technology [0003] Generally speaking, a liquid crystal display (hereinafter referred to as LCD) is a device that displays color video by receiving three signals R (red), G (green), and B (blue). LCD is widely used in commercial portable terminals, and it can normally support 5:6:5 mode or 6:6:6 mode. The 5:6:5 mode LCD uses 5 bits, 6 bits, and 5 bits to represent R, G, and B, which can represent about 65,000 colors respectively...

AI Technical Summary

Problems solved by technology

[0016] However, in the prior art system, since the data between D15-D10 in the 16-bit data input by the first clock is not used in receiving the data constituting one pixel, the efficiency of data conversion is reduced

For this reason, a "2×N×M" CPU clock is used to transfer the entire video of the "N×M" size to the LCD block, thereby increasing the corresponding data transfer time

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