Synchronous semiconductor device, and inspection system and method for the same
a semiconductor device and synchronous technology, applied in the direction of instruments, fault location, and fault increase, can solve the problems of more effective testing of electrical stress, degeneration of voltage and short circuit between wirings, and permanent defects, so as to achieve the effect of effective burn-in stress test and higher efficiency of applying electrical stress
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second embodiment
[0059] Now second preferred embodiment of the present invention will be described in greater details herein below. In the schematic block diagram of circuit shown in FIG. 4, the command latch circuit 100, test mode discriminator circuit 60, and user mode sequence circuit 410 will have the same structure as the circuits described in the preceding first preferred embodiment. In the second embodiment, a precharge controller circuit 30 is added thereto for inputting a precharge control signal TPRE in a burn-in stress test to a test mode sequence circuit 20 to invoke a precharging operation.
[0060] A typical example of word line controller circuit in accordance with the second preferred embodiment in FIG. 5 includes a test mode sequence circuit 20 comprised of only one NAND gate 21. The user mode sequence circuit 410 is composed of one NAND gate 72 and a internal timer 73 to input the output signals from the NAND gate 72. The output signals form the test mode sequence circuit 20 and the u...
third embodiment
[0068] Now a third preferred embodiment of the present invention will be described in greater details herein below. The command latch circuit 100, test mode discriminator circuit 60, user mode sequence circuit 410, and test mode sequence circuit 20 in the schematic block diagram of circuitry of FIG. 7 are identical to those described in the foregoing second preferred embodiment of the present invention. In the present third embodiment, a CLK falling edge detector circuit 40 and a precharging controller circuit 50 are incorporated instead of the precharge controller circuit 30 for inputting a precharging control signal TXPRE in synchronism with a falling edge of the external clock CLK to the test mode sequence circuit 20 to invoke a precharging operation, in the burn-in stress test.
[0069] In a typical example of word line controller circuit in accordance with the third preferred embodiment shown in FIG. 8, in a similar manner to the foregoing second embodiment, the output signal of t...
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