Synchronous semiconductor device, and inspection system and method for the same

a semiconductor device and synchronous technology, applied in the direction of instruments, fault location, and fault increase, can solve the problems of more effective testing of electrical stress, degeneration of voltage and short circuit between wirings, and permanent defects, so as to achieve the effect of effective burn-in stress test and higher efficiency of applying electrical stress

Inactive Publication Date: 2005-05-26
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances the efficiency of electrical stress application during burn-in stress tests, allowing for a more effective screening of defective products by increasing the duration of the activated state, thus improving the overall testing process.

Problems solved by technology

Any residual ionized movable impurity in the oxide of a semiconductor device may lead in practice to a permanent defective such as degenerated capacity to voltage and short circuit between wirings due to the displacement of such impurity caused by thermal or electric stresses.
This indicates that a test that can apply the electrical stress more effective than this percentage is not achievable and that any attempts to further saving time of test may fail.
In the burn-in stress test on the other hand, the maximum performance may not be achieved by the limitation in the testing environment and the like, thus in general the synchronous semiconductor device has enough margins to operate with respect to the frequency of the external clock CLK used in the test.
This concludes that the electrical stress may not effectively applied because of the small duty rate in the given time t1 that the word lines are activated.

Method used

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  • Synchronous semiconductor device, and inspection system and method for the same
  • Synchronous semiconductor device, and inspection system and method for the same
  • Synchronous semiconductor device, and inspection system and method for the same

Examples

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second embodiment

[0059] Now second preferred embodiment of the present invention will be described in greater details herein below. In the schematic block diagram of circuit shown in FIG. 4, the command latch circuit 100, test mode discriminator circuit 60, and user mode sequence circuit 410 will have the same structure as the circuits described in the preceding first preferred embodiment. In the second embodiment, a precharge controller circuit 30 is added thereto for inputting a precharge control signal TPRE in a burn-in stress test to a test mode sequence circuit 20 to invoke a precharging operation.

[0060] A typical example of word line controller circuit in accordance with the second preferred embodiment in FIG. 5 includes a test mode sequence circuit 20 comprised of only one NAND gate 21. The user mode sequence circuit 410 is composed of one NAND gate 72 and a internal timer 73 to input the output signals from the NAND gate 72. The output signals form the test mode sequence circuit 20 and the u...

third embodiment

[0068] Now a third preferred embodiment of the present invention will be described in greater details herein below. The command latch circuit 100, test mode discriminator circuit 60, user mode sequence circuit 410, and test mode sequence circuit 20 in the schematic block diagram of circuitry of FIG. 7 are identical to those described in the foregoing second preferred embodiment of the present invention. In the present third embodiment, a CLK falling edge detector circuit 40 and a precharging controller circuit 50 are incorporated instead of the precharge controller circuit 30 for inputting a precharging control signal TXPRE in synchronism with a falling edge of the external clock CLK to the test mode sequence circuit 20 to invoke a precharging operation, in the burn-in stress test.

[0069] In a typical example of word line controller circuit in accordance with the third preferred embodiment shown in FIG. 8, in a similar manner to the foregoing second embodiment, the output signal of t...

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Abstract

The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a synchronous semiconductor device and an inspection system for synchronous semiconductor devices, and more particularly to a synchronous semiconductor device and an inspection system for synchronous semiconductor device, incorporating a function to effectively perform burn-in stress test for screening defective products. [0003] 2. Description of the Prior Art [0004] Any residual ionized movable impurity in the oxide of a semiconductor device may lead in practice to a permanent defective such as degenerated capacity to voltage and short circuit between wirings due to the displacement of such impurity caused by thermal or electric stresses. In order to eliminate these potentially problematic devices as defectives from final products prior to shipping, a burn-in stress test is performed. The burn-in stress test consists of a screening test by applying thermal and electric stresses to t...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G01R31/28G01R31/317G11C8/08G11C11/401G11C29/00G11C29/06G11C29/34
CPCG01R31/31701G11C29/34G11C8/08G11C29/00
InventorSUGAMOTO, HIROYUKITANAKA, HIDETOSHIOGAWA, YASUSHIGE
OwnerSOCIONEXT INC