Digital control logic circuit having a characteristic of time hysteresis

Inactive Publication Date: 2005-06-09
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The proposed solution achieves glitch-free signal transitions in both directions, minimizing glitches when the digital control signal transitions from '1' to '0' and from '0' to '1', and allows for various hysteresis characteristics by incorporating a state machine.

Problems solved by technology

As a result, the conventional time hysteresis circuit shows a problem to have only one-way characteristic of time hysteresis wherein the input signal A(t) transits from “1” to “0” or from “0” to “1”.

Method used

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  • Digital control logic circuit having a characteristic of time hysteresis
  • Digital control logic circuit having a characteristic of time hysteresis
  • Digital control logic circuit having a characteristic of time hysteresis

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first embodiment

[0025]FIG. 3 is a diagram illustrating time hysteresis circuit according to the present invention. The time hysteresis circuit in FIG. 3 comprises two time hysteresis units 30, 31 connected in series and an inverter 12 to output terminal of the time hysteresis unit 31.

[0026] The time hysteresis unit 30 which receives the input signal A(t) delays it for the delay time “td1”, and then outputs the output signal B(t). The time hysteresis unit 31 receives the output signal B(t) and delays it for the delay time “td2”. The inverter 12 inverts an output signal from the time hysteresis unit 31 and outputs an output signal C(t). According to the status of the output signal C(t), the inverter I2 may be preferably incorporated into the time hysteresis circuit.

[0027] Here, the internal configurations of the time hysteresis units 30, 31, respectively, may be designed as shown in FIG. 1. Accordingly, the operating relationship will be described in detail without explanation on the internal config...

second embodiment

[0039]FIG. 6 is a diagram illustrating time hysteresis circuit according the present invention.

[0040] The time hysteresis circuit comprising delay unit 60 and state machine 61 receives the input signal A(t) and outputs an output signal D(t).

[0041] The delay unit 60 delays the input signal A(t) for the delay time “td3”, and outputs the delayed signal A(t-td3).

[0042] The state machine 61 receives the input signal A(t) and the delayed signal A(t-td3) from the delay unit 60, and output the out put signal D(t). At this time, the state machine 61 changes the state according to the transition of the input signal A(t) and the delayed signal A(t-td3).

[0043] The state machine 61 is desirable to be configured with two SR-latches (not shown) or to be embodied with two D-flip flops (not shown).

[0044]FIG. 7 is a diagram for illustrating the operation of the state machine 61 In FIG. 6.

[0045] The state machine 61 uses two input signals A(t), A(t-td3) and has four states S0, S1, S3, S3.

[0046] ...

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Abstract

The present invention discloses a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, comprising a first time hysteresis unit, a second time hysteresis unit and an inverter. The first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level. The second time hysteresis unit has the characteristic of time hysteresis connected to the first hysteresis in series when the input signal transits from the second level to the first level.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a control logic circuit having a characteristic of time hysteresis in a semiconductor memory device, and more particularly to a control logic circuit having a characteristic of time hysteresis when the signals transit from “1” to “0” and from “0” to “1” by connecting two time hysteresis circuits in series. [0003] 2. Description of the Prior Art [0004] In general, a digital control logic circuit in a semiconductor memory device generates a glitch (short pulse) during delay time as it passes through a delay unit. A time hysteresis circuit is used for eliminating such a glitch. [0005] The time hysteresis circuit has a characteristic of time hysteresis, and the characteristic of time hysteresis controls transition of a digital control signal for a predetermined time when the digital control signal transits from “1” to “0” or from “0” to “1”. Such characteristic of time hysteresis may eli...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H03L7/00G11C11/22H03K3/037H03K5/12H03K5/1252
CPCH03K5/1252H03L7/00
InventorYOON, SANG SIC
OwnerSK HYNIX INC