Method and apparatus to generate circuit energy models for macros containing internal clock gating

a technology of macros and energy models, applied in the direction of electric/magnetic computing, analogue processes for specific applications, instruments, etc., can solve the problems of difficult accurate power simulations, and achieve the effect of accurate power simulations

Inactive Publication Date: 2006-07-27
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006] To produce these energy tables the specific macro must be represented in a computer program. From this model circuit power simulations can be generated for any combination of input switching factor percentages and clock activation percentages. Accurate power simulations are difficult when a macro contains internally generated clock activate signals. With multiple clock gating inputs and internal clock activate signals the clock activation percentage can be estimated by connecting

Problems solved by technology

Accurate power simulations are difficult when a macro contains internally generated clock activate signals.

Method used

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  • Method and apparatus to generate circuit energy models for macros containing internal clock gating
  • Method and apparatus to generate circuit energy models for macros containing internal clock gating
  • Method and apparatus to generate circuit energy models for macros containing internal clock gating

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Embodiment Construction

[0019] In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electromagnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art.

[0020] The power simulations of these macros are accomplished by computer software programs. Typically, one computer program sets up the circuits and the inputs into the circuits and another computer program...

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Abstract

A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro containing internal clock gating. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain internal clock gating and multiple clock gating inputs. To achieve accurate power estimates a voltage supply is connected to each clock activate signal. Energy tables are then created based upon the macro's input switching factor percentage and clock activation percentage. These power tables are generated from a minimum number of power simulations. By incorporating internally generated clock activate signals into the power estimations the macro energy tables are much more accurate.

Description

FIELD OF THE INVENTION [0001] The present invention relates generally to power estimation in chip design, and more particularly, to generating energy tables for macros containing internal clock gating. DESCRIPTION OF THE RELATED ART [0002] System power is an important issue in Very Large-Scale Integration (VLSI) chip design. Battery life, packaging cost, and power delivery cost are factors that are affected by chip power consumption. Power estimates are used in place of methodical testing or methodical simulation to save time and resources. These estimates can be produced from a minimal number of simulations or tests. To lower the power consumption of a particular chip design it is important that the power estimates are accurate. [0003] Chip power estimation starts at the macro level. A chip is made up of many macros, which are small circuits within the chip. Each macro within a chip generates an energy model or rule. Referring to FIG. 1 of the drawings, reference numeral 100 is a b...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F17/5022G06F30/33
InventorCHAUDHRY, RAJATNEELY, JAMES SCOTTSTASIAK, DANIEL LAWRENCE
OwnerIBM CORP