Diffusion barrier and method of formation thereof

Inactive Publication Date: 2013-04-11
GLOBALFOUNDRIES SINGAPORE PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is related to a method and device for forming a structure or semiconductor device with reduced diffusion of elements between different regions. This is achieved by forming a diffusion barrier with cavities that serve as a barrier to the diffusion of elements between the regions. The technical effect is the improved reliability and performance of semiconductor devices and devices including the structure.

Problems solved by technology

Diffusion of dopant atoms and other atoms in integrated circuit (IC) structures is responsible for a number of problems associated with the fabrication and long term stability of IC structures.
For example, electrical characteristics of static random access memory (SRAM) structures are adversely affected by lateral diffusion in polysilicon of dopant such as phosphorus from strongly n+ doped regions.
However, substantial diffusion of dopant still occurs during subsequent thermal processing such as polysilicon reoxidation processes and rapid thermal annealing (RTA).
Furthermore, diffusion of extrinsic dopant and source / drain dopant into the channel region can occur, again resulting in an adverse effect on electrical characteristics of the structure.
However, such measures may introduce further problems such as gate induced drain leakage (GIDL) and a lack of dopant activation.

Method used

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  • Diffusion barrier and method of formation thereof
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  • Diffusion barrier and method of formation thereof

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Embodiment Construction

[0014]FIG. 1 is a schematic illustration in cross-section of a structure 100 formed during a process of fabricating a semiconductor device, such as a static random access memory (SRAM) device. Forming other types of devices or structures are also useful.

[0015]The structure has a silicon substrate 102 having a plurality of, for example, P-type doped well regions (P-wells) 104 and a plurality of N-type doped well regions (N-wells) 106. Respective P-wells 104 and N-wells 106 are separated by shallow trench isolation (STI) regions 108.

[0016]The substrate 102 has a layer of a gate dielectric medium 110 formed thereover. In the embodiment of FIG. 1, the layer of gate dielectric medium 110 is a layer of nitrided silicon oxide. In some embodiments, the layer of gate dielectric medium 110 is silicon oxide or any other suitable gate dielectric medium. In some embodiments, layer 110 is formed from a high dielectric constant (“high-k”) gate dielectric material.

[0017]The layer of gate dielectric...

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Abstract

A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Description

FIELD OF THE INVENTION[0001]The present invention relates to diffusion barriers and to a method of forming a diffusion barrier. In particular but not exclusively the invention relates to a diffusion barrier in an integrated circuit device and a method of forming a diffusion barrier in an integrated circuit device.BACKGROUND[0002]Diffusion of dopant atoms and other atoms in integrated circuit (IC) structures is responsible for a number of problems associated with the fabrication and long term stability of IC structures. For example, electrical characteristics of static random access memory (SRAM) structures are adversely affected by lateral diffusion in polysilicon of dopant such as phosphorus from strongly n+ doped regions. This causes N− / P+ junctions between NFET and PFET devices to shift towards the PFET device.[0003]In order to ameliorate the problem, a shallower n+ pre-doped implant and a smaller N+implanted area have been adopted. However, substantial diffusion of dopant still ...

Claims

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Application Information

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IPC IPC(8): H01L29/66H01L23/532
CPCH01L21/823807H01L29/7833H01L21/266H01L21/823878H01L21/823814H01L29/1083H01L21/823842H01L29/32H01L21/823871H01L21/26506H01L2924/0002H01L21/3223H01L23/532H01L29/66477H01L2924/00H01L21/26513H01L21/76224H01L27/088H01L29/0649H01L29/36H01L29/66537
InventorTAN, SHYUE SENGTEO, LEE WEECHONG, YUNG FUQUEK, ELGINCHU, SANFORD
OwnerGLOBALFOUNDRIES SINGAPORE PTE LTD