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Stack die structure for stress reduction and facilitation of electromagnetic shielding

a technology of stress reduction and die structure, applied in the field of integrated circuits, can solve problems such as stress failures in semiconductor devices and materials used, and achieve the effect of reducing thermal stress

Inactive Publication Date: 2014-04-01
MARVELL ASIA PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent is about a device and method designed to reduce thermal stress on a packaged semiconductor device caused by the thermal expansion of the insulating material used to encapsulate the semiconductor device. The device includes a lead frame, a first semiconductor device, a second semiconductor device, and insulating material encapsulating the first and second semiconductor devices. The second semiconductor device is not electrically active and does not electrically interact with any other electrical component outside of the device. The first semiconductor device has a unique coefficient of thermal expansion, which is different from the second semiconductor device, and the insulating material also has a unique coefficient of thermal expansion. This difference in coefficients of thermal expansion helps to minimize the stress applied to the first semiconductor device by the expanding insulating material. The device is manufactured by coupling the first semiconductor device to a die pad and coupling the second semiconductor device to the top of the first semiconductor device, and the insulating material is formed around the first and second devices to provide insulating and physical protection.

Problems solved by technology

Thermal variations during normal operations of a semiconductor device can cause stress failures in the semiconductor device and the materials used to package the semiconductor device.
Over time, stress or fatigue due to the expansion and contraction of the various materials can result in structural damage to the semiconductor device which may prevent the semiconductor device from functioning as intended.

Method used

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  • Stack die structure for stress reduction and facilitation of electromagnetic shielding
  • Stack die structure for stress reduction and facilitation of electromagnetic shielding
  • Stack die structure for stress reduction and facilitation of electromagnetic shielding

Examples

Experimental program
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Effect test

Embodiment Construction

[0016]FIG. 1 illustrates a side view of a packaged wire bonded device (device) 100 in a Quad Flat no lead (QFN) package configuration. However, the QFN configuration is used for purposes of illustration only and not limitation. The techniques to reduce and isolate stress and electromagnetic interference described herein may be used in any type of semiconductor packaging device. For example, the techniques may be used with, but are not limited to, Quad Flat Packages (QFP), Ball Grid Array (BGA), Thin & Fine Pitch BGA (TFBGA), molded Flip-Chip Chip Scale Package (FCCSP), and Multi-Row QFN (MRQFN).

[0017]The packaged wire bonded device 100 of FIG. 1 includes a lead frame comprised of a die pad 102 and a plurality of leads 104. The die pad 102 supports the semiconductor component 106, and is secured or coupled to the die pad 102 by adhesive material 108. In one embodiment, the semiconductor component 106 is a semiconductor device having one or more electrical circuit to perform one or mo...

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PUM

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Abstract

Embodiments of the present disclosure describe a packaged semiconductor device that reduces stress on a semiconductor device caused by thermal expansion of the insulating material used in the packaged semiconductor device. In one embodiment, an inactive semiconductor device is coupled to the top of active semiconductor device. Both the inactive and active devices are encapsulated by the insulating material. The configuration of the inactive device is selected based on its ability to absorb the expansion of the insulating material at operating temperature.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This disclosure claims priority to U.S. Provisional Patent Application No. 61 / 429,343, filed Jan. 3, 2011, the entire specification of which is hereby incorporated by reference in its entirety for all purposes, except for those sections, if any, that are inconsistent with this specification.TECHNICAL FIELD[0002]Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly, to techniques, structures, and configurations of semiconductor chip packaging.BACKGROUND[0003]The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.[0004]Thermal characteristics of...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/49
CPCH01L23/49513H01L29/0657H01L24/32H01L2224/32245H01L23/4334H01L24/48H01L2224/73265H01L23/49575H01L2224/48465H01L24/49H01L23/315H01L2224/73215H01L2224/48247H01L23/49H01L2924/3025H01L2224/32145H01L24/73H01L23/552H01L23/562H01L24/29H01L24/33H01L24/83H01L24/85H01L2224/29011H01L2224/29076H01L2224/29078H01L2224/2919H01L2224/29195H01L2224/32012H01L2224/32057H01L2224/33181H01L2224/48105H01L2224/48257H01L2224/8385H01L2224/92247H01L2225/0651H01L2225/06568H01L2924/10155H01L2924/351H01L2924/181H01L2924/00014H01L2924/00H01L2924/00012H01L2224/45099H01L2224/05599
Inventor KAO, HUAHUNGNGO, THOMASLIOU, SHIANN-MING
Owner MARVELL ASIA PTE LTD