Stack die structure for stress reduction and facilitation of electromagnetic shielding
a technology of stress reduction and die structure, applied in the field of integrated circuits, can solve problems such as stress failures in semiconductor devices and materials used, and achieve the effect of reducing thermal stress
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[0016]FIG. 1 illustrates a side view of a packaged wire bonded device (device) 100 in a Quad Flat no lead (QFN) package configuration. However, the QFN configuration is used for purposes of illustration only and not limitation. The techniques to reduce and isolate stress and electromagnetic interference described herein may be used in any type of semiconductor packaging device. For example, the techniques may be used with, but are not limited to, Quad Flat Packages (QFP), Ball Grid Array (BGA), Thin & Fine Pitch BGA (TFBGA), molded Flip-Chip Chip Scale Package (FCCSP), and Multi-Row QFN (MRQFN).
[0017]The packaged wire bonded device 100 of FIG. 1 includes a lead frame comprised of a die pad 102 and a plurality of leads 104. The die pad 102 supports the semiconductor component 106, and is secured or coupled to the die pad 102 by adhesive material 108. In one embodiment, the semiconductor component 106 is a semiconductor device having one or more electrical circuit to perform one or mo...
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