Dynamic self-adaptive bus arbiter based on microprocessor-on-chip

An on-chip multi-processor and dynamic self-adaptive technology, applied in electrical digital data processing, instruments, etc., can solve problems such as unpredictability and complex priority setting, achieve good bus bandwidth, reduce bus waiting time, and improve system performance. Effect

Active Publication Date: 2009-07-15
南京宁麒智能计算芯片研究院有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the complex priority setting in high-performance MPSoC, it is difficult to predict

Method used

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  • Dynamic self-adaptive bus arbiter based on microprocessor-on-chip
  • Dynamic self-adaptive bus arbiter based on microprocessor-on-chip
  • Dynamic self-adaptive bus arbiter based on microprocessor-on-chip

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Embodiment 1

[0027] A kind of dynamic adaptive bus arbiter based on on-chip multiprocessor system according to the present invention on the shared AMBA-AHB bus of four processors, see appendix Figure 7 The modules included are: interface control module 1 conforming to the AMBA-AHB bus standard, random number generation module 2, dynamic "lottery" number generation module 3, timer module 4 and Lottery bus arbitration module 5; interface control module 1 is responsible for and For communication on the bus, the timer module 4 sends an interrupt request to the dynamic "lottery ticket" number generation module 3 according to the current processor waiting for the bus situation, thereby determining the number of "lottery tickets" of each main device at present, and the random number generation module 2 generates the number that meets the range requirements. Random number, the Lottery bus arbitration module 5 generates the ID number of the processor that obtains the right to use the bus according ...

Embodiment 2

[0034]A hierarchical bus system including a shared system bus and four processors as master devices, the system includes: four first-level buses independently occupied by each processor for access to its private memory; bus bridge , which is used for the connection between the first-level bus and the second-level bus, and controls the processor's access to different buses; the shared memory can be accessed by four processors, and is used for synchronization and data exchange between different processors; and the second The second-layer bus is the bus shared by each processor, including: a dynamic adaptive bus arbitrator, the number of "lottery tickets" held by each processor represents the ratio of the bus bandwidth occupied by each processor, and a weighted random algorithm is used to control the processor's performance on the system. The use priority of the bus, in response to the activation of the interrupt signal of the internal timer of the arbitrator, continuously increas...

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Abstract

The invention discloses a dynamic self-adaptive bus arbiter based on an on-chip multiprocessor system, comprising an interface control module, a random number generation module, a dynamic "lottery ticket" number generation module, a timer module and a Lottery bus arbitration module; the random number generation The scope of the module receiving interface control module signal output random number is configured as the total number of "lottery tickets" under the bus application requirements of each processor; the dynamic "lottery ticket" number generation module stores the initial number of "lottery tickets" held by each processor, and responds to The activation of the interrupt signal generated by the timer module; the Lottery bus arbitration module controls the use priority of the system bus according to the number of "lottery tickets" held by each processor. The invention reduces the algorithm complexity, reduces the bus waiting time of each processor, can better control the bus bandwidth occupied by each processor, improves the system performance, and has important reference value for the design of multi-processor system on chip.

Description

technical field [0001] The present invention relates to an on-chip multiprocessor system applied to a bus architecture, in particular to a high-performance on-chip multiprocessor system that has strict requirements on the bus bandwidth ratio occupied by processors and real-time requirements, specifically A dynamic adaptive bus arbiter for on-chip multiprocessor systems. Background technique [0002] In recent years, Multi-Processor System-on-a-Chip (MPSoC), which supports high-speed parallel computing and multimedia applications, has developed rapidly. The performance of an MPSoC system using a shared bus architecture depends largely on the efficiency of the arbitration mechanism. The arbiter is responsible for assigning the priority of each processor to access shared resources, solving the competition caused by multiple processors sharing resources, allocating shared resources reasonably and efficiently and ensuring the optimal overall system performance. [0003] The sys...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/362
Inventor 李丽徐懿杨盛光何书专李伟高明伦张冰张宇昂
Owner 南京宁麒智能计算芯片研究院有限公司
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