Dynamic self-adaptive bus arbiter based on microprocessor-on-chip

An on-chip multi-processor, dynamic self-adaptive technology, used in electrical digital data processing, instruments, etc., can solve the problems of complex and unpredictable priority setting, and achieve the goal of reducing bus latency, improving bus bandwidth, and improving overall performance. Effect

Active Publication Date: 2008-03-19
南京宁麒智能计算芯片研究院有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the complex priority setting in high-performance MPSoC, it is difficult to predict

Method used

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  • Dynamic self-adaptive bus arbiter based on microprocessor-on-chip
  • Dynamic self-adaptive bus arbiter based on microprocessor-on-chip
  • Dynamic self-adaptive bus arbiter based on microprocessor-on-chip

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Embodiment 1

[0027] A kind of dynamic self-adaptive bus arbiter based on on-chip multiprocessor system according to the present invention on the shared AMBA-AHB bus of four processors, see accompanying drawing 7, the module that comprises has: Meet AMBA-AHB bus Standard interface control module 1, random number generation module 2, dynamic "lottery" number generation module 3, timer module 4 and Lottery bus arbitration module 5; interface control module 1 is responsible for communication with the bus, and timer module 4 according to the current processing The device waits for the bus situation to send an interrupt request to the dynamic "lottery ticket", and the number generation module 3 determines the number of "lottery tickets" of each main device at present. The random number generation module 2 produces a random number that meets the range requirements, and the Lottery bus arbitration module 5 is based on the above The output of the module generates the ID number of the processor that ...

Embodiment 2

[0034] A hierarchical bus system including a shared system bus and four processors as master devices, the system includes: four first-level buses independently occupied by each processor for access to its private memory; bus bridge , which is used for the connection between the first-level bus and the second-level bus, and controls the processor's access to different buses; the shared memory can be accessed by four processors, and is used for synchronization and data exchange between different processors; and the second The second-layer bus is the bus shared by each processor, including: a dynamic adaptive bus arbitrator, the number of "lottery tickets" held by each processor represents the ratio of the bus bandwidth occupied by each processor, and a weighted random algorithm is used to control the processor's performance on the system. The use priority of the bus, in response to the activation of the interrupt signal of the internal timer of the arbitrator, continuously increa...

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Abstract

The present invention discloses a dynamic self-adapting bus arbiter based on a SOC (system on a chip) multiprocessor system, consisting of an interface control module, a stochastic number producing module, a dynamic lottery number producing module, a timer module and a lottery bus arbitration module. The stochastic number producing module receives the range of the stochastic number outputted by the signal of the interface control module and configures the stochastic number into a total lottery number applied to and demanded by each processor to the bus. The dynamic lottery number producing module stores the initial number of the lottery held by each processor and responds to an activation of the interrupted signal produced by the timer module. The lottery bus arbitration module controls the using priority of the system bus according to the number of the lottery held by each processor. The present invention lowers the arithmetic complexity, reduces the bus waiting time of each processor and can better control the bandwidth occupied by each processor, thereby enhancing the system performance and providing a significant reference value for the design of a SOC multiprocessor system.

Description

technical field [0001] The present invention relates to an on-chip multiprocessor system applied to a bus architecture, in particular to a high-performance on-chip multiprocessor system that has strict requirements on the bus bandwidth ratio occupied by processors and real-time requirements, specifically A dynamic adaptive bus arbiter for on-chip multiprocessor systems. Background technique [0002] In recent years, Multi-Processor System-on-a-Chip (MPSoC), which supports high-speed parallel computing and multimedia applications, has developed rapidly. The performance of an MPSoC system using a shared bus architecture depends largely on the efficiency of the arbitration mechanism. The arbiter is responsible for assigning the priority of each processor to access shared resources, solving the competition caused by multiple processors sharing resources, allocating shared resources reasonably and efficiently and ensuring the optimal overall system performance. [0003] The sys...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/362
Inventor 李丽徐懿杨盛光何书专李伟高明伦张冰张宇昂
Owner 南京宁麒智能计算芯片研究院有限公司
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