Dynamic self-adaptive bus arbiter based on microprocessor-on-chip

Abstract

The present invention discloses a dynamic self-adapting bus arbiter based on a SOC (system on a chip) multiprocessor system, consisting of an interface control module, a stochastic number producing module, a dynamic lottery number producing module, a timer module and a lottery bus arbitration module. The stochastic number producing module receives the range of the stochastic number outputted by the signal of the interface control module and configures the stochastic number into a total lottery number applied to and demanded by each processor to the bus. The dynamic lottery number producing module stores the initial number of the lottery held by each processor and responds to an activation of the interrupted signal produced by the timer module. The lottery bus arbitration module controls the using priority of the system bus according to the number of the lottery held by each processor. The present invention lowers the arithmetic complexity, reduces the bus waiting time of each processor and can better control the bandwidth occupied by each processor, thereby enhancing the system performance and providing a significant reference value for the design of a SOC multiprocessor system.

Description

technical field [0001] The present invention relates to an on-chip multiprocessor system applied to a bus architecture, in particular to a high-performance on-chip multiprocessor system that has strict requirements on the bus bandwidth ratio occupied by processors and real-time requirements, specifically A dynamic adaptive bus arbiter for on-chip multiprocessor systems. Background technique [0002] In recent years, Multi-Processor System-on-a-Chip (MPSoC), which supports high-speed parallel computing and multimedia applications, has developed rapidly. The performance of an MPSoC system using a shared bus architecture depends largely on the efficiency of the arbitration mechanism. The arbiter is responsible for assigning the priority of each processor to access shared resources, solving the competition caused by multiple processors sharing resources, allocating shared resources reasonably and efficiently and ensuring the optimal overall system performance. [0003] The sys...

AI Technical Summary

Problems solved by technology

Due to the complex priority setting in high-performance MPSoC, it is difficult to predict

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