Minimum value comparing method in LDPC decoding and realization device thereof

Abstract

The invention discloses a minimum value comparing method in LDPC decoding and a realization device thereof. The method comprises the steps of: S1, utilizing a first-stage comparing unit to sequence n input numbers, taking every adjacent two numbers as a group according to the sequence for comparing respectively, and obtaining n / 2 groups of minimum values and sub-minimum values; S2, utilizing a mid-stage comparing unit to group the n / 2 groups of minimum values and sub-minimum values, count every two adjacent groups into one group according to the sequence so as to obtain n / 4 new groups, and comparing the numbers in each new group so as to obtain n / 4 groups of minimum values and sub-minimum values; S3, repeating S2 till obtaining a minimum value, a sub-minimum value and a minimum position pointer of the n input numbers; and S4, utilizing a final-output-stage unit to conduct gating output operation. The method adopts a comparison operation unit based on the minimum position pointer, realizes high-speed operation, saves hardware resources and can conduct standardized structuring grading flow design, reduce the time delay of operation logics and improve the operation speed.

Description

technical field [0001] The invention relates to the technical field of digital information transmission, in particular to a minimum value comparison method based on a minimum value position pointer in LDPC decoding and an implementation device thereof. Background technique [0002] LDPC (low density parity-check, low-density parity-check) code is a kind of linear block code based on sparse parity check matrix construction. It was first proposed by Gallager in 1962 and re-proposed by MacKay in 1996. LDPC codes have great application potential and will be widely used in deep space communications, optical fiber communications, satellite digital video, digital watermarking, magnetic / optical / holographic storage, mobile and fixed wireless communications, cable modulators / demodulators and digital subscriber lines application. Especially in the field of digital information transmission technology, LDPC code has become the first choice in the fourth generation mobile communication c...

AI Technical Summary

Problems solved by technology

Depend on figure 2 It can be seen from the figure that each output is obtained by comparing the minimum value of other inputs except the corresponding input. Such a large-scale comparison module takes up more hardware resources, and at the same time makes the logic operation delay larger. The arithmetic unit can only work at a lower clock frequency, which further restricts the decoding rate

Moreover, such a structure is not conducive to the realization of hierarchy

As the number of inputs increases, the hardware resource usage will increase dramatically

Images