Multiply-add method and multiply-add apparatus

An adder and multiplication technology, applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of logarithmic growth, increase complexity, waste layout area, etc., achieve power consumption reduction, improve operation The effect of speed and space saving

Active Publication Date: 2011-03-16
NAT UNIV OF DEFENSE TECH
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AI Technical Summary

Problems solved by technology

Although the traditional fused multiply-adder designed in this way is very fast, the delay on the critical path increases logarithmically with the increase in

Method used

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  • Multiply-add method and multiply-add apparatus
  • Multiply-add method and multiply-add apparatus

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Embodiment Construction

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] Such as figure 1 As shown, the multiplier-adder of the present invention includes a Bush encoding logic unit 10, a partial product generation logic unit 11, an addend block logic unit 12, an adder 15, a high bit prediction logic unit 14, an improved Wallace tree unit 13 and Splicing logic unit 16, it adopts the multiplication and addition method of the present invention, the step of this multiplication and addition method is: the multiplier produces some control signals 10A by the Bush encoding unit 10, and the multiplicand produces the input of the logic unit 11 as the partial product, according to the control Signal 10A yields a partial product 11A. The addend passes through the addend block logic unit 12 to obtain three outputs, which are respectively: a low bit truncation part 12A, a middle part 12B and a high bit truncati...

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Abstract

The invention disclose a multiply-add method and multiply-add apparatus, the method comprises the following steps: (1) a multiplier generates a plurality of control signals through a Bush coding logical unit, a multiplicand serves as the input of a partial product generating logical unit, and a partial product is generated; (2) an addend obtains a lower-order intercepting part, an intermediate part and a higher-order intercepting part through an addend partitioning logical unit; the lower-order intercepting part, the intermediate part and the partial product serve as the input of an improved Wallace tree unit, the obtained result serves as the input of an adder, and a lower-order result and a control signal are generated; 3 the higher-order intercepting part obtains a higher-order result through a higher-order forecasting logical unit; and (4) the lower-order result and the higher-order result obtains a final result through a matching logical unit. The multiply-add apparatus comprise the Bush coding logical unit, the partial product generating logical unit, the addend partitioning logical unit, the adder, the higher-order forecasting logical unit, the improved Wallace tree unit and the matching logical unit. The invention has the advantages of simple and compact structure, low cost, quick arithmetic speed, stabilization, reliability, and the like.

Description

technical field [0001] The invention mainly relates to the field of multiply-add processors, in particular to a multiply-add method and a multiply-add device. Background technique [0002] The traditional multiplication and addition fusion is to put the addend as a partial product at the bottom of the Wallace tree of the multiplier. When performing a rectangular layout, using a traditional Wallace tree multiply-adder will result in a large waste of area. Mounir Bohsali (Many Boselli) and Michael Doan (Michel Doan) proposed a method to transform the traditional multiplier Wallace tree and obtain a new type of Wallace tree . Since the Wallace tree of the multiplier is relatively regular, it is easy to divide the Wallace tree of the multiplier by using this method to achieve the purpose of optimization. However, the traditional multiplication and addition fusion is to add the addend as a partial product to the Wallace tree of the multiplier, which leads to an irregular struc...

Claims

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Application Information

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IPC IPC(8): G06F7/57
Inventor 彭元喜谢刚杨惠陈书明刘衡竹郭阳孙永节刘宗林龚国辉鲁建壮许邦建
Owner NAT UNIV OF DEFENSE TECH
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