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Any clock implementation method of program clock reference (PCR) counter

An implementation method and a technology of a counter, which are applied in the field of transmission of digital multimedia programs, and can solve problems such as system flexibility limitation

Inactive Publication Date: 2011-05-18
深圳速浪数字技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] Since the processing of the existing MPEG-2 standard program transport stream (TS stream) must run under the 27MHz system clock stipulated by the MPEG-2 standard, this brings some limitations to the flexibility of the system

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  • Any clock implementation method of program clock reference (PCR) counter
  • Any clock implementation method of program clock reference (PCR) counter
  • Any clock implementation method of program clock reference (PCR) counter

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Embodiment Construction

[0025] Such as image 3 As shown, the PCR counter module of the embodiment of the present invention is formed by cascading three parts: DDS counter, PCR_base counter, and PCR_ext counter, wherein the accumulation step of the DDS counter is determined by the adjustable input system_frequency.

[0026] When the system clock is higher than 27MHz, its specific implementation structure is as follows Figure 4 As shown, the whole module includes 9-bit adjustable input system_frequency, adder A, 10-bit register Reg1, adder B, 9-bit register Reg2, comparator CMP, selector MUX, subtractor Sub, adder C, 33-bit register Reg3. f s For a system clock greater than 27MHz, the step value system_frequency=2 9 ×27M / f s , according to the used system clock f s Adjustment, the value of register Reg1 is accumulated with step value C, overflow1 is connected to the overflow value of the highest bit of register Reg1, the comparator CMP compares the value in register Reg2 with 300, when the value...

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Abstract

The invention relates to the transmission of digital multimedia programs, in particular to a program clock reference (PCR) adjusting method of transport stream (TS) in a moving picture experts group-2 (MPEG-2) standard. The PCR counter is formed by sequentially cascading a direct digital synthesis (DDS) counter, a PCR-ext counter and a PCR-base counter, wherein the DDS counter, the PCR-ext counter and the PCR-base counter are realized by programmable logic; accumulated stepping of the DDS counter is determined by adjustable input; accumulated stepping of the PCR-ext counter is generated by the DDS counter; and when the count value of the PCR-ext counter reaches 300, the count value of the PCR-base counter is added by 1. By the any clock very large scale integrated circuit (VLSI) implementation method of the PCR counter, a PCR counter module can run under any system clock so as to adapt to application under different conditions. The method has the advantages of simple circuit, high adaptability and the like.

Description

technical field [0001] The invention relates to the transmission of digital multimedia programs, in particular to a PCR (Program Clock Reference, program reference clock) adjustment method for TS streams in the MPEG-2 standard. Background technique [0002] The MPEG-2 standard is a key standard in multimedia communication. It can provide broadcast-level digital video for broadcasting and cable TV networks. The processing of the MPEG-2 standard program transport stream (TS stream) is a research topic in digital TV systems. focus. When multiplexing MPEG-2 program TS streams, two key technologies, PCR adjustment and PID replacement, are involved. [0003] According to the MPEG-2 standard, the encoder uses a 27MHz system clock to generate time stamps indicating when audio and video are correctly displayed and decoded. A 27MHz system clock is also used for decoding at the receiving end, so that the synchronization of the codec end can be guaranteed. In the TS stream, the progr...

Claims

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Application Information

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IPC IPC(8): H04N21/242H04N7/24
Inventor 王宏远沈志江威涂重文王亚峰许森黄育雄
Owner 深圳速浪数字技术有限公司
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