Method for scheduling multipliers and canceling pulse generators
A technology for offsetting pulses and multipliers, applied in the field of communications, can solve problems such as insufficient allocation of multiplier resources, affecting PC-CFR output PAR performance, and discarding error signals.
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Embodiment 1
[0021] figure 1 A flow chart of a method for scheduling multipliers according to an embodiment of the present invention is shown, the method is applied in the process of generating a cancellation pulse, and the method includes the following steps:
[0022] Step S102, according to the relationship between the current error signal and the next error signal, the flag of the current error signal is set as a discarding flag or a non-discarding flag;
[0023] The flag of the error signal in this embodiment occupies 1 bit, and the flag can be set before or after the error signal, as long as the offset pulse generator can identify it. For convenience, the discarding flag can be set to 0, and the non-discarding flag can be set to 1.
[0024] When setting the identification of the error signal, it is only necessary to compare the current error signal with the next adjacent error signal, for example: if the amplitude of the current error signal is greater than or equal to the amplitude ...
Embodiment 2
[0037] This embodiment is illustrated by taking the implementation on FPGA as an example, wherein the identification of the error signal is set as follows:
[0038] First, the error signal is sequentially delayed by the length of the filter coefficient for clock cycles. When an error signal is found, it is judged whether the distance between the error signal and the next error signal is smaller than the length of the filter coefficient. If so, the amplitude is greater than the amplitude of the next error signal. , set the flag of the error signal to 1, such as figure 2 As shown; if the distance between the error signal and the next error signal is less than the filter coefficient length, and the magnitude of the error signal is smaller than the magnitude of the next error signal, set the flag of the error signal to 0, such as image 3 shown; if there is no next error signal within the filter coefficient length range, the error signal is also marked as 1, such as Figure 4 sh...
Embodiment 3
[0047] Figure 6 A structural block diagram of a canceling pulse generator according to an embodiment of the present invention is shown, including:
[0048] Mark setting module 62, set the sign of current error signal according to the relationship between current error signal and next error signal as discarding mark or non-discarding mark;
[0049] Multiplier scheduling module 64, for when the number of multipliers is less than or equal to specified value (such as 1 or 2), judge whether the sign of current error signal is to discard sign, if yes, discard current error signal, if not, for The current error signal is assigned a multiplier.
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