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Memory access processing method and controller

A memory and controller technology, applied in the field of communication, can solve the problems of dynamic random access memory (DRAM) periodic refresh occupation, large memory bandwidth, read and write operations, etc., to achieve simple design, save occupied bandwidth, and reduce the number of refreshes Effect

Active Publication Date: 2013-04-03
BEIJING HUAWEI DIGITAL TECH
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Problems solved by technology

[0005] The embodiment of the present invention provides a memory access processing method and a controller, which are used to solve the problem that the periodic refresh of DRAM occupies a relatively large memory bandwidth and causes delays in read or write operations

Method used

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  • Memory access processing method and controller
  • Memory access processing method and controller

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Embodiment Construction

[0031] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0032] figure 1 This is a schematic flowchart of Embodiment 1 of the memory refresh processing method provided by the present invention, such as figure 1 As shown, the method includes:

[0033] S101. Use a counter to time the time between two adjacent accesses of each row of the DRAM, and obtain the timing result T 1 ;

[0034] S102. If ...

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Abstract

The embodiment of the invention provides a memory access processing method and a controller. The method includes the following steps: a counter is adopted to count the time between two neighboring accesses of each line of a dynamic random memory (DRAM) to acquire a timing result T1; and if the time T1 corresponding to one line of the DRAM is greater than the refresh cycle T2 of the DRAM, then the line is accessed and processed to be refreshed. In the embodiment of the invention, the time between two neighboring accesses of each line is counted, refresh operation does not need to be carried out anymore if the line is accessed in the refresh cycle, so that the frequency of refresh is decreased, and thereby the bandwidth occupied by cyclic refresh is saved; for a line which is not accessed in the refresh cycle, a one-time access mode is adopted to substitute for refresh, special refresh operation does not need to be taken into consideration, and thereby the design is simpler.

Description

Technical field [0001] The embodiments of the present invention relate to communication technology, and in particular, to a memory access processing method and controller. Background technique [0002] With the increasing speed of network equipment, board-level signal integrity (SI) / power integrity (PI) design is more difficult, and the bandwidth requirements for memory are getting higher and higher. [0003] In the prior art, Dynamic Random Access Memory (DRAM) is a common system memory. Since the charge of the capacitor in the DRAM is lost every time, the data can only be stored for a short time. In order to save data, the DRAM needs to be refreshed periodically, that is, the DRAM is charged. [0004] In the process of implementing the embodiments of the present invention, the inventor discovered that in the prior art, the refresh operation, read operation, or write operation of the DRAM all occupy the same interface. When refresh operation is performed, read operation or write op...

Claims

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Application Information

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IPC IPC(8): G06F13/16
Inventor 王国民
Owner BEIJING HUAWEI DIGITAL TECH
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