Method and device for quickening HPI accessing speed and improving HPI accessing accuracy

Abstract

The invention discloses a method and device for quickening the HPI accessing speed and improving the HPI accessing accuracy. The method is characterized by including the steps of designing an HPI accessing timing sequence through a programmable logic device, enabling addresses and data to be sent in a 32-bit command mode when a user carries out accessing, enabling the HPI accessing timing sequence to automatically generate a timing sequence required by two times of half-word accessing, releasing a bus after the operation is completed, and judging an HRDY when the accessing is carried out. According to the method and device, the HPI accessing timing sequence is designed through the programming capacity of the programmable logic device, the aim that only one time of reading-writing is required when DSP address space is read and written for one time is achieved, and therefore the speed is high; in addition, due to the fact that the interruption condition does not exist in the two times of operation, the condition of the HPI wrong operation can be avoided, the defects that the HPI operation can not be stopped through HRDY signals, and the accessing can be carried out only through fixed delay are overcome, the HPI accessing accuracy is improved, and meanwhile the HPI accessing speed is quickened by one time by combining the two times of operation into the one time of operation.

Description

technical field [0001] The invention relates to a method for improving the access speed and accuracy of the HPI interface, and a device for improving the access speed and accuracy of the HPI interface. Background technique [0002] The HPI interface is a 16-bit wide parallel interface unique to the TIC6000 series chips of Texas Instruments, which provides a channel for the host to access the entire address space of the DSP chip. HPI has three registers, HPIC (control register) is used for interface setting, HPIA (address) and HPID (data) registers are used to store access address and read and write data. These three registers are 32-bit, so reading and writing registers requires two 16-bit operations. The HPI interface automatically merges two adjacent operations into one operation. If the two operations are not completed, DSP will have unpredictable errors. [0003] TI chips are widely used. Many applications use the HPI interface to realize the access between the host com...

AI Technical Summary

Problems solved by technology

The advantage of this is that the entire HPI operation will not be suspended because the HRDY line of the HPI interface is invalid, causing the system to crash. The disadvantage is that it cannot guarantee that the HPI read and write access is correct because it does not judge whether the HPI is ready.

[0004] The current HPI access is two accesses to realize the access of a DSP address space, and there is no protection for the two HPI operations. When the HPI fails, because the HRDY signal is not judged, the next access is automatically performed by a delay method, not only A lot of time is wasted for each operation, and there is no prompt for HPI operation even if there is an error