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Tristable RS trigger capable of supporting multiple value logic

A multi-valued logic and flip-flop technology, applied in the direction of logic circuits, parts and electrical components that generate electrical pulse circuits, etc., can solve the problem that RS flip-flops cannot obtain 11 states, etc., and achieve the effect of simple and easy structure.

Inactive Publication Date: 2014-04-02
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to solve the problem that the existing RS flip-flop cannot obtain the 11 state, and propose a tri-stable RS flip-flop supporting multi-valued logic, which can obtain three stable states of 01, 10, and 11

Method used

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  • Tristable RS trigger capable of supporting multiple value logic
  • Tristable RS trigger capable of supporting multiple value logic
  • Tristable RS trigger capable of supporting multiple value logic

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Embodiment Construction

[0024] The content of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0025] The logical symbol of the tristable RS flip-flop of the present invention is as figure 1 As shown, its internal circuit is as figure 2 As shown, it includes three NAND gates G1, G2 and G3, and two AND gates AND1 and AND2. Wherein, G1 and G2 respectively include three input terminals and one output terminal, G3 includes four input terminals and one output terminal, AND1 and AND2 respectively include two input terminals and one output terminal. The two inputs of the tristable RS flip-flop are S and R, and the two outputs are Q and N, which are the outputs of G1 and G2 respectively.

[0026] The three input terminals of G1 are a1, b1, c1 respectively, and one output terminal is Q,

[0027] The G2 includes three input terminals a2, b2, c2 and an output terminal N,

[0028] The G3 includes four input terminals a3, b3, c3, d3 and on...

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Abstract

The invention relates to a tristable RS trigger capable of supporting the multiple value logic and belongs to the technical field of digital circuits. The tristable RS trigger capable of supporting the multiple value logic comprises three NAND gates (G1, G2 and G3) and two AND gates (AND1 and AND2), wherein two inputs of the tristable RS trigger are S and R, and two outputs of the tristable RS trigger are Q and N; the inputs of four input ends of the G3 are S, R, Q and N respectively; three input ends of the G1 are respectively connected with the output end of the G3, the S and the output end of the AND2; three input ends of the G2 are respectively connected with the output end of the G3, the R and the output end of the AND1; two input ends of the AND1 are connected with the output Q of the G1, and two input ends of the AND2 are connected with the output N of the G2. The tristable RS trigger can obtain 01, 10 and 11 stable states and realize the multiple value logic, is simple in structure and practical, and can be used for providing a technical support for a molecular computer based on a digital circuit.

Description

technical field [0001] The invention relates to a three-stable RS flip-flop supporting multi-valued logic, belonging to the technical field of digital circuits. Background technique [0002] Molecular computing is based on multi-valued logic, and the tri-stable RS flip-flop is one of the basic components for building molecular computing based on digital logic circuits. Molecular computing uses DNA encoded by bases (A, T, C, G) as "data", DNA biochemical reactions as "operations", DNA before the reaction as the "input" of the problem, and DNA after the reaction as the "output". After polynomial time "operation", the "answer" is finally obtained and read out. [0003] Molecular computing is a space-based processing model, which can generate, process and store exponential data at the same time through efficient information encoding and huge parallel storage and processing systems, and realize exponentially accelerated calculation and time-space complexity conversion. [0004]...

Claims

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Application Information

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IPC IPC(8): H03K19/00H03K3/01
Inventor 李艳梅马天宝任会兰宁建国余文
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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