A VLSI Synthesis Method

Abstract

The present invention particularly relates to a VLSI synthesis method of a very large scale integrated circuit. The VLSI synthesis method of the VLSI adopts a bottom-up synthesis strategy. After the sub-modules of the lowest level are synthesized, the modules of the upper level are synthesized until the top layer of the chip; the special script is compared with the general script. In combination, there is also an error / report extraction script. Each setting script is not directly read into the DC platform, but is managed by the built executable script. By reading the executable script, each setting script is called in turn. The VLSI synthesis method of the VLSI adopts the down-top strategy to synthesize the VLSI, and divides the integrated platform settings into dedicated settings and general settings through script control, which makes the maintenance of the integrated platform simpler and more convenient. In addition, the increased information Extract setup scripts to automate the processing of log files and synthesis results.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a VLSI synthesis method for very large scale integrated circuits. Background technique [0002] With the continuous development of digital integrated circuits, the complexity of the chip is getting deeper and deeper, and the scale is getting bigger and bigger. The synthesis work is an important bridge to communicate the front-end logic design and the back-end physical design. The speed and quality of the synthesis work seriously affect the development of the back-end physical design, which has an important impact on the tape-out of the chip. Therefore, it is necessary to build a reasonable and efficient comprehensive environment to speed up the comprehensive work. For VLSI, there are two important problems in the synthesis process: one is that there are many layers of chip logic, and each layer contains several sub-modules; the other is that the scale is large,...

AI Technical Summary

Problems solved by technology

For VLSI, there are two important problems in the synthesis process: one is that the chip has many logic layers, and each layer contains several sub-modules; the other is that the scale is large, possibly hundreds of millions of circuits.

If the full-chip synthesis is performed, a large amount of memory is required, which puts high demands on the server. At the same time, it takes a long time, and various settings cannot be corrected in time, which seriously affects the quality and quantity of the netlist submission.

[0003] Very large-scale integrated circuits, the scale is too large, and the overall chip synthesis usually adopts a top-down top-down strategy. This synthesis method has problems such as high resource requirements, large time overhead, and high iteration costs. At the same time, there are many chip levels and module differentiation, which cannot be adopted. Synthesize and optimize timing with the exact same synthesis constraints

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