Burr-free switching circuit for supporting multi-way clock

Abstract

The invention provides a burr-free switching circuit for supporting a multi-way clock. The burr-free switching circuit comprises a register, an AND gate, a first selector, a register group, a decoding circuit, a multi-clock interlock circuit and a clock selector; the decoding circuit realizes decoding of a one-hot encoding mode on a clock selection signal, and a log2N bit clock selection signal is translated into a decoding result of N bit one-hot encoding, so that the uniqueness and excludability of an effective clock enable signal can be guaranteed; meanwhile, the multi-clock interlock circuit processes the decoding result according to the currently outputted clock enable; if the currently outputted clock enable is not equal to the decoding result, then all clock enables are firstly closed, and then the decoding result is used as a new clock enable signal to open corresponding clocks, so that burr-free switching of a clock signal can be realized. The burr-free switching circuit for supporting the multi-way clock provided by the invention can realize burr-free switching of N paths of input clocks, support random switching orders, and provide greater flexibility for a work pattern of the whole circuit.

Description

technical field [0001] The invention belongs to the field of reliability of integrated circuits, relates to a burr-free clock switching circuit, in particular to a burr-free switching circuit supporting multiple clocks. Background technique [0002] In order to realize intelligent management of power consumption, a clock switching circuit is essential in contemporary complex System on Chip (SOC for short). Based on the support of the clock switching circuit, the operating frequency of a certain module or subsystem in the SOC can be adjusted according to the workload, thereby intelligently reducing power consumption. For example, the Ethernet MAC supports the communication rate of 10 / 100 / 1000M. Based on different communication rates, dynamically changing the clock frequency of the MAC can reduce the power consumption of the chip to the greatest extent. In addition, in order to make the SOC work mode more flexible and rich, the circuit should also support the switching of dif...

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Problems solved by technology

[0003] Patents "A Clock Switching Circuit" (ZL200710098961.0), "A Clock Switching Circuit" (ZL200810067535.5), "Clock Switching Circuit" (ZL200810068164.2) and "A Clock Switching Method and Clock Switching Device" ( ZL201010560049.4) and others have disclosed glitch-free clock switching schemes, but the above-mentioned schemes only support the dynamic switching of two clocks

[0004] The patent "a clock switching device" (ZL201410310730.1) proposes a glitch-free switching scheme that supports multiple clocks, but this scheme only allows sequential switching of the clock frequency from high to low or from low to high, and does not support jumping clock switching

[0005] The glitch-free clock switching scheme in the prior art cannot avoid the influence of signal instability and noise on the circuit, and there is a problem that it does not support the skip-type glitch-free switching of multiple clocks.

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