Forward error correction circuit, high-speed serial transceiver and programmable logic device

A forward error correction, high-speed serial technology, applied in electrical components, coding components, error correction/detection using linear codes, etc., can solve the problems of low performance of HSST transmission bit error rate and reduce the transmission bit error rate. , the effect of reducing circuit area and complexity

Inactive Publication Date: 2017-06-13
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The invention provides a forward error correction circuit, a high-speed serial transceiver and a programmable logic device, so as to solve the problem of low performance of the existing HSST transmission bit error rate

Method used

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  • Forward error correction circuit, high-speed serial transceiver and programmable logic device
  • Forward error correction circuit, high-speed serial transceiver and programmable logic device
  • Forward error correction circuit, high-speed serial transceiver and programmable logic device

Examples

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no. 1 example

[0023] figure 1 A schematic structural diagram of the HSST circuit provided for the first embodiment of the present invention, by figure 1 It can be seen that, in this embodiment, the HSST circuit provided by the present invention includes: the physical medium connects the PMA circuit 11 and the protocol coding sublayer PCS circuit 12, and the forward error correction FEC circuit 13, and the forward error correction FEC circuit 13 is arranged on the physical medium Connect between the PMA circuit 11 and the protocol coding sublayer PCS circuit 12, for using the BCH code to correct errors, in the sending direction, receive the data to be sent obtained by the protocol coding sublayer PCS circuit 12 for processing and clock domain conversion, and send The data to be sent is encoded, after the encoding, the parity bit is added to the information bit, and then transmitted to the physical medium to connect to the PMA circuit 11. In the receiving direction, the data to be processed o...

no. 2 example

[0034] The present invention will be further explained in combination with specific application scenarios.

[0035] High Speed ​​Serial Transceiver (HSST: High Speed ​​Serial Transceiver) is the foundation of today's wireless communications, cloud computing and big data centers. As the speed of HSST continues to increase, its transmission bit error rate performance is greatly challenged. Therefore, by integrating the FEC technology in the HSST, the transmission bit error rate can be reduced through the FEC technology. FEC can reconstruct erroneous data at the receiving end to reduce the bit error rate. The sending end of the FEC circuit generates verification data through encoding technology; the receiving end verifies the received data through decoding technology, and can reconstruct error data through the received verification data. The errors in high-speed serial communication are mostly burst random errors, so FEC needs to have a strong ability to correct burst random er...

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Abstract

The invention provides a forward error correction circuit, a high-speed serial transceiver and a programmable logic device. The high-speed serial transceiver comprises a PMA circuit, a PCS circuit and an FEC circuit, and the FEC circuit is arranged between the PMA circuit and the PCS circuit and is used for performing error correction by using a BCH code. According to the high-speed serial transceiver provided by the invention, the FEC circuit is added to the traditional HSST circuit, so that the transmission error rate can be effectively reduced, an FEC function is realized by using the BCH code, since the BCH code runs in a binary domain, a BCH code decoding circuit is much simpler than an RS code decoding circuit, and the complexity of circuit design can be effectively reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a forward error correction circuit, a high-speed serial transceiver and a programmable logic device. Background technique [0002] HSST (High Speed ​​Serial Transceiver, high-speed serial transceiver) is the foundation of today's wireless communication, cloud computing, and big data centers. As the speed of HSST continues to increase, its transmission bit error rate performance is greatly challenged. Contents of the invention [0003] The invention provides a forward error correction circuit, a high-speed serial transceiver and a programmable logic device to solve the problem of low performance of the existing HSST transmission bit error rate. [0004] The invention provides a FEC (Forward Error Correct, forward error correction) circuit for a high-speed serial transceiver, which is arranged between the physical medium connection PMA circuit and the protocol coding subl...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H03M13/15H03M13/29H04L1/00
CPCH03M13/152H03M13/2909H04L1/0041H04L1/0045H04L1/0057
Inventor刘应
OwnerSHENZHEN PANGO MICROSYST CO LTD