Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a non-display area and a display area, wherein the non-display area comprises a first non-display area anda second non-display area, the display area comprises a normal display area and a wire distribution area; the first non-display area surrounds the normal display area, the normal display area surrounds the wire distribution area, the wire distribution area surrounds the second non-display area, and the second non-display area comprises a perforation area. According to the technical scheme, data leads corresponding to subpixels which are simultaneously charged are arranged in an overlapping manner, so that the number of the data leads arranged in a same layer of the wire distribution area is reduced, the area of the wire distribution area is reduced, and a narrow frame design between the second non-display area and the normal display area is realized. Moreover, since the number of the dataleads in the same layer of the wire distribution area is reduced, a linear distance between the adjacent data leads is increased, so that the coupling capacitance between the adjacent data leads arranged on the same layer is reduced.

Description

technical field [0001] The present invention relates to the field of display technology, and more specifically, to an array substrate and a display panel. Background technique [0002] With the rapid development of narrow bezels of display screens, full screens have emerged as the times require. Since the display screen usually has components such as a front camera, a speaker, an indicator light, and a sensor, holes need to be opened in the display area of ​​the full screen. [0003] Usually, the data lines corresponding to the sub-pixels located under the opening need to bypass the opening, and the size of the wiring area surrounding the opening on the full screen is limited, so that the line spacing between the data lines located in the wiring area is smaller than that of the display. The line spacing between adjacent data lines in the wiring area leads to a large coupling capacitance between adjacent data lines in the wiring area. [0004] Therefore, how to provide an a...

AI Technical Summary

Problems solved by technology

[0003] Usually, the data lines corresponding to the sub-pixels located under the opening need to bypass the opening, and the size of the wiring area surrounding the opening on the full screen is limited, so that the line spacing between the data lines located in the wiring area is smaller than that of the display. The line spacing of adjacent data lines in the area, which leads to a large coupling capacitance between adjacent data lines in the wiring area

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