Hardware sequencer system and design method for split path in polar code decoding

A technology of hardware sorting and design method, which is applied in the field of communication, can solve problems such as the reduction of sorting clock frequency, and achieve the effect of low decoding delay and saving sorting time

Active Publication Date: 2019-03-01
CHINA UNIV OF GEOSCIENCES (WUHAN)
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  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a hardware sequencer system and design method for path splitting in polar code decoding, aiming at the defect in the prior art that the frequency of the sorting clock is significantly reduced when the input path increases, using The time complexity of bucket sorting is independent of the size of the input data, and a low-latency, low-complexity hardware sorter system is designed

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  • Hardware sequencer system and design method for split path in polar code decoding
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  • Hardware sequencer system and design method for split path in polar code decoding

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[0044] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation manners of the present invention will now be described in detail with reference to the accompanying drawings.

[0045] Please refer to figure 1 , which is the overall architecture of the sorter design system, specifically including 4 modules, namely the input module 11, the bucket sorting module 12, the sorting network module 13 and the output module 14, wherein:

[0046] The input module 11 is used to input 2L decoding paths to be sorted; the decoding paths include L original decoding paths and L split decoding paths, wherein L takes a value of 2 n , n≥1 and n is an integer;

[0047] Wherein, each decoding path includes a metric value for evaluating the pros and cons of the path. The lower the metric value, the better the decoding path. The metric value set of the initial decoding path before splitting is defined for:

[0048...

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Abstract

The invention provides a hardware sequencer system and design method for a split path in polar code decoding. The system and the design method provided by the invention have the beneficial effects that during a decoding process of a polar code, the paths of fixed bits do not need to be sorted, so that the sorting time of the fixed bits is saved; in addition, only the information bits need to be sorted, the delay time of a sequencer is basically independent of an input path quantity, and when the path quantity is relatively large, the decoding delay rate is still relatively low.

Description

technical field [0001] The present invention relates to the communication field, and more specifically relates to a hardware sequencer system and a design method for path splitting in polar code decoding. Background technique [0002] Polar codes are currently the only coding method that can be theoretically proven to reach the Shannon limit in binary discrete memoryless channels. SCL serial cancellation decoding is a low-complexity decoding method. The SCL serial cancellation list decoding method is an improved method of the SC decoding method, which can achieve better bit error rate performance. There are L decoding paths in SCL decoding, and each decoding path has a metric value for evaluating the quality of the path. In the case of information bits, every time a bit is decoded, each decoding path must be split into two, that is, L paths will be extended to 2L paths. Through the sorter, select L paths with the smallest metric value among the 2L paths, and keep L paths ...

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Application Information

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IPC IPC(8): H03M13/13
CPCH03M13/13
Inventor王家豪胡振宇叶敦范蒋哲栋
OwnerCHINA UNIV OF GEOSCIENCES (WUHAN)