Static random access memory device, redundant circuit thereof, and semiconductor device
A static random access, redundant circuit technology, applied in the field of redundant circuits, can solve the problems of complexity and high cost, and achieve the effect of simple structure, reducing the total cost of the die, and reducing the size of the die
Active Publication Date: 2020-11-10
POWERCHIP SEMICON MFG CORP
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Problems solved by technology
[0025] There are problems such as that the configuration becomes complicated by adding the redundant circuit to the memory IC, and high cost is incurred.
However, there is no SRAM device in the prior art that does not use a fuse member to form a redundant circuit.
Method used
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Embodiment Construction
[0095] Embodiments of the present invention will be described below. In addition, the same code|symbol is attached|subjected to the same or the same component.
[0096] As described in the above-mentioned problems of the prior art, there are problems such as that the configuration becomes complicated and the cost is high due to the addition of the redundant circuit to the memory IC. Specifically, the fuse member for implementing the redundant circuit of the memory IC needs to be developed by itself or purchased from another company as intellectual property (intellectual property, IP). At this time, a special structure or a special procedure and the cost rises. Furthermore, since the area of the fuse member cannot be reduced in accordance with the miniaturization, the increase in area when a large number of fuses are used can be regarded as a major factor of cost increase. If a redundant circuit that does not require a fuse member can be realized, unique effects such as red...
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The present invention provides a redundant circuit for a static random access memory device, the redundant circuit and a semiconductor device thereof. The static random access memory device includes a plurality of input and output memory units. The redundant circuit includes: a plurality of pairs of first transistors and second transistors, each connected between a power supply voltage and a power supply terminal of each input-output memory unit, the first transistors and the second transistors are connected in parallel with each other, and the first transistors have Greater mutual conductance than the second transistor; and a redundant control circuit, when the first transistor is turned off and the second transistor is turned on, the voltage of the power supply terminal of each input and output memory unit is detected, when the voltage of the power supply terminal is automatically When the predetermined reference voltage drops by a predetermined value or more, the I / O memory cell is determined to be in a defective state, and the I / O memory cell in the defective state is redundantly replaced with a normal I / O memory cell.
Description
technical field [0001] The present invention relates to a redundant circuit for a Static Random Access Memory (SRAM) device, an SRAM device including the redundant circuit, and a semiconductor device including the SRAM device. Background technique [0002] In a semiconductor storage device such as a memory integrated circuit (hereinafter, the integrated circuit is referred to as an IC (integrated circuit)), redundant circuits are added to repair malfunctions and improve yield. Here, the redundant circuit is implemented, for example, by using a tester component such as a memory tester device or a built-in self-test (Built-In Self Test, BIST) circuit, and a fuse component. [0003] As the fuse member, there are the following types. [0004] (1) Laser fuse (laser fuse); [0005] (2) Electrical fuses; and [0006] (3) Flash memory (flash memory). [0007] [Prior art literature] [0008] [Patent Document] [0009] [Patent Document 1] Japanese Patent Laid-Open No. 2008-19926...
Claims
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IPC IPC(8): G11C11/413
CPCG11C29/022G11C29/4401G11C29/702G11C29/76G11C29/787G11C11/419G11C11/418G11C7/12G11C8/10G11C8/08H10B10/18
Inventor木原雄治
OwnerPOWERCHIP SEMICON MFG CORP