A Realization Method of Vector Aggregate Load Instruction

An implementation method and instruction technology, which are applied in the implementation field of vector aggregated load instructions, can solve the duplication of the micro-operation management function of a vector buffer unit and the function of the launch queue, and cannot support multiple vector aggregated load instructions and multiple vector aggregated loads at the same time. Instructions cannot be executed in parallel, so as to reduce the number of micro-operations, reduce Perm operations, and improve program performance

CN110908716BActive Publication Date: 2022-02-08NAT UNIV OF DEFENSE TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2022-02-08

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Abstract

The present invention relates to the technical field of microprocessor design, and in particular to a method for implementing a vector aggregation load instruction. The corresponding element number is sent to the instruction queue; after the operand is ready, the single-element loading micro-operation is sent to the storage pipeline to obtain data; the obtained data is written into the corresponding element of the corresponding data cache item; all data cache items After the element data is written, the result data is written from the data cache to the result bus, and the execution of the vector aggregation load instruction is completed. The invention can effectively improve the execution performance of the vector aggregation load instruction, and at the same time can maximize the use of the path of the common load instruction, is suitable for high-performance out-of-order superscalar microprocessors, and has the advantages of simple implementation and high performance.
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Description

technical field

[0001] The invention relates to the technical field of microprocessor design, in particular to a method for realizing a vector aggregation load instruction. Background technique

[0002] In order to adapt to the development of application programs and improve the efficiency of program execution, a variety of vector extensions have been added to mainstream instruction sets. Taking full advantage of the parallelism of vector operations can improve system performance. In vector extension, there is a type of vector aggregate load instruction (Gather Load, denoted as GLoad), which is very different from ordinary load instructions. Such as figure 1 As shown in (a) in (a), the ordinary load instruction loads the data of a continuous address in the storage space into the register. And for vector aggregate load instructions, such as figure 1 As shown in (b) in (b), the address of each element of the vector is different. This instruction needs to fetch an element f...

Examples

Embodiment Construction

[0034] Such as image 3 As shown, the implementation steps of the implementation method of the vector aggregation load instruction in this embodiment include:

[0035] 1) Split the vector aggregate loading instruction into multiple common loading micro-operations according to the size of the vector elements;

[0036] 2) Send the split normal load micro-operation to the instruction queue;

[0037] 3) Waiting for the source operand of the common load micro-operation to be ready in the instruction queue, and launching the corresponding common load micro-operation to the storage pipeline after the source operand is ready and carrying the vector element number;

[0038] 4) Execute common loading micro-operations for a single element;

[0039] 5) Judging whether the execution is successful, if the execution is successful, jump to the next step; otherwise, the launch queue needs to choose an opportunity to re-transmit the memory access operation of the element to the pipeline to ob...