TLB exception handling method and device, electronic equipment and storage medium

Abstract

The embodiments of the invention provide a TLB exception handling method and device, electronic equipment and a storage medium, belonging to the technical field of computers. The method comprises thesteps of acquiring a first parameter required for processing a TLB exception; modifying a second parameter in a preset universal register into the first parameter; taking the first parameter as a calling parameter of a super calling interface, and performing skipping from a virtual machine with the TLB exception to a host machine through the super calling interface; and carrying out TLB exceptionprocessing in the host machine according to the first parameter. According to the method and the device, when the TLB exception occurs in the virtual machine, the first parameter required for processing the TLB exception is transmitted to the host machine through the super calling interface, and at the moment, the virtual machine exits, so the host machine can process the TLB exception according to the first parameter. The TLB exception is processed by the host machine, so the exit frequency of the virtual machine can be reduced, the overhead of TLB exception processing is reduced, and the time for processing the TLB exception is shortened.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a TLB exception processing method, a data sharing device, an electronic device and a storage medium. Background technique [0002] The MIPS (Microprocessor without interlocked piped stages, microprocessor without internal interlocked pipeline stage) architecture is a concise, optimized, and highly scalable reduced instruction set (RISC) processor architecture. In the class virtualization (also known as paravirtualization) scenario based on the MIPS architecture, in order to improve data access efficiency and reduce repeated page table lookups, a TLB (Translation Lookaside Buffer, translation detection buffer) is introduced to cache the recently used Page table entries, that is, the mapping relationship between GVA (Guest Virtual Address, the virtual address of the virtual machine) to GPA (Guest PhysicalAddress, the physical address of the virtual machine) and the mapping relati...

AI Technical Summary

Problems solved by technology

However, in specific applications, in the class virtualization scenario based on the MIPS architecture, the relevant instructions of the TLB exception handling in the Guest (virtual machine) mode cannot be realized. Therefore, in the prior art, every time the Guest TLB exception handling occurs related instructions, an abnormal error will be reported in the Host (host), and then it is necessary to exit the Guest, and then simulate these instructions through the Host to realize the functions of these instructions

[0004] However, handling TLB exceptions requires exiting the Guest multiple times, and the overhead of exiting the Guest is relatively large

In addition, the Host needs to interrupt the TLB exception handling process of the Guest many times to simulate the TLB exception handling instructions, which will prolong the TLB exception handling process, making it very time-consuming to process TLB exceptions in Guest mode.

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