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Word line output gating circuit

A gating circuit and word line technology, applied in the direction of electrical digital data processing, static memory, special data processing applications, etc., can solve the problems of XDEC circuit design complexity, area cost, etc., achieve simple structure, layout and wiring, and save logic complexity The effect of reducing the degree and simplifying functional requirements

Pending Publication Date: 2020-11-27
澜智集成电路(苏州)有限公司
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AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a word line output gating circuit to solve the problems of XDEC circuit design complexity and area cost faced by advanced large-capacity storage technology

Method used

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Embodiment Construction

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

[0025] In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the pr...

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Abstract

The invention discloses a word line output gating circuit. According to the invention, two transmission pipes of the same type are used; one PMOS transistor is used for transmitting positive and negative high voltages; the other PMOS transistor is used for biasing a word line in a non-enabling state; the distances between the high-voltage P trap isolating ring of the PMOS tube and the high-voltageN trap and the deep N trap of the NMOS tube in the prior art are saved from the aspect of layout occupied area, the high-voltage P trap isolating ring and the deep N trap isolating ring of the NMOS tube are also saved, and only one high-voltage N trap isolating ring is used as a substrate. Besides, the same PMOS transistor is used for transmitting positive and negative high voltages, so that thelogic complexity and the layout area of the related sector output control circuit can be saved, the functional requirements on a peripheral drive circuit are simplified, the structure and the layout wiring of the word line decoder control circuit become simple, and the occupied layout area can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor memory chip design, in particular to a word line output gating circuit. Background technique [0002] The word line decoder control circuit (XDEC) in the non-volatile flash memory technology Nor Flash memory mainly provides word line (WL) decoding for the memory array (Memory Array), and reads (Read), writes (PGM), erases The voltage signals in (ER) and other modes are selected and output to the WL of the array unit (Array Cell 1) according to the mode control signal and address information. Therefore, XDEC is the only modular circuit in memory chips that increases linearly with memory capacity. However, the smaller the process size of the Cell, the smaller the height of the Array, which limits the height of the XDEC on the layout. If the original circuit area remains unchanged, the X direction of the XDEC will be further expanded. At the same time, the narrow space will also increase the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/08G06F30/392G06F30/394
CPCG11C16/08G06F30/392G06F30/394
Inventor 马力
Owner 澜智集成电路(苏州)有限公司
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