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A vmac high-speed address learning method and electronic equipment

An address learning and V-UMAC technology, applied in the field of VMAC high-speed address learning methods and electronic equipment, can solve the problems of limited update of VMAC address learning speed, achieve a simple and fast refresh mechanism, improve data processing rate, and reduce data error processing rate effect

Active Publication Date: 2022-03-25
FENGHUO COMM SCI & TECH CO LTD +1
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

Since the update logic of the V-State state table is serial, that is, after the application of the previous data message is processed, it is not known whether the application of the next data message reaches the VMAC application threshold, which limits the speed of VMAC address learning. Update of the V-State status table

Method used

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  • A vmac high-speed address learning method and electronic equipment
  • A vmac high-speed address learning method and electronic equipment
  • A vmac high-speed address learning method and electronic equipment

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Embodiment Construction

[0049] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0050] In order to improve the VMAC address learning speed and realize the high-speed pipeline processing of VMAC address learning, the present invention proposes a structure of "Control Cache", "Data Cache" and Main memory, and proposes a "Control Cache" refresh mechanism to reduce the high-speed processing data error processing rate.

[0051] The structure of the Cache is a first-in-first-out...

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Abstract

The invention discloses a VMAC high-speed address learning method. In order to improve the VMAC address learning speed and realize the high-speed pipeline processing of the VMAC address learning, the invention proposes a structure of "Control Cache", "Data Cache" and Main memory, and proposes "Control Cache" refresh mechanism to reduce data error processing rate caused by high-speed processing. Realize high-speed pipeline processing of VMAC address learning and merge of redundant operations, improve access effectiveness, ensure data consistency, and increase the speed of VMAC address learning. The present invention can reduce the influence of main memory reading and writing delay on system design, and "data cache" can reduce the delay of obtaining the latest data; it can reduce the influence of operating frequency on system design, and the working frequency is increased. In order to meet the timing requirements, storage The data becomes longer from read to write, and the "Data Cache" can merge the temporary state of the write operation. The invention also provides corresponding electronic equipment.

Description

technical field [0001] The invention belongs to the technical field of IP (Internal Protocol, network protocol) communication, and more specifically, relates to a VMAC high-speed address learning method and electronic equipment. Background technique [0002] The VMAC function belongs to the MAC (Media Access Control, Media Access Control) address security function. In the current IP access network based on Layer 2 Ethernet forwarding as the core, the untrustworthy MAC address of end users may cause MAC address spoofing. In the uplink direction, when the access device receives the message sent by the user side, it will convert the "untrusted" terminal user source MAC address into a "trusted" VMAC (Virtual Media Access Control, virtual media access control) address, And learn the VMAC address, and then forward it to the upper network. In the downlink direction, when a packet received from the network side is sent to the user port, the address learning table is queried, and t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L61/00
CPCH04L2101/622
Inventor 张艳鲁鹏杨彦波
Owner FENGHUO COMM SCI & TECH CO LTD
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