CT detector data transmission structure and CT detector data transmission method based on source synchronization LVDS-SERDES

Abstract

The invention belongs to the technical field of CT, and particularly relates to a CT detector data transmission structure and method based on source synchronization LVDS-SERDES. The CT detector data transmission structure comprises a data aggregation module and M rows of detector groups, wherein M is greater than or equal to 2; each row of detector groups is in communication connection with the data aggregation module; each row of detector groups comprises N detector modules, wherein N is greater than or equal to 2; in each row of detector groups, the detector modules are connected in series; and each detector module carries an FPGA chip. An FPGA chip is carried on the data aggregation module. The invention provides a novel series-parallel combined data transmission mode. According to the invention, the universal differential pins of the FPGA chip are used, so that the design is not limited by the number of Transeiver any more, and logic resources in the FPGA chip can be efficiently utilized. The method can save the cost, and has the characteristics of unified architecture and high expandability.

Description

technical field

[0001] The invention belongs to the field of CT technology, and in particular relates to a source synchronous LVDS-SERDES-based CT detector data transmission structure and a data transmission method. Background technique

[0002] In existing detectors, large quantities of data are transmitted between substrate clusters through the Transceiver, a dedicated hardware resource built into the FPGA. Since the wide-body detector is composed of dozens or even hundreds of modules, and each module is equipped with an FPGA chip, the work to be done by the FPGA chip is very simple, that is, to collect data from multiple ADs, and aggregate these data for backward level sending. In theory, you only need to use a very cheap FPGA chip with low logic density, but in reality, because the existing solutions use a dedicated high-speed serial transceiver Transceiver for data transmission, and the existing low-end FPGA chips are not Equipped with Transceiver.

[0003] In additi...

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